Datasheet
Programmer’s Model
ARM7TDMI Data Sheet
ARM DDI 0029E
3-14
Open Access
3.9.10 Exception priorities
When multiple exceptions arise at the same time, a fixed priority system determines
the order in which they are handled:
Highest priority:
1 Reset
2 Data abort
3 FIQ
4 IRQ
5 Prefetch abort
Lowest priority:
6 Undefined Instruction, Software interrupt.
Not all exceptions can occur at once:
Undefined Instruction and Software Interrupt are mutually exclusive, since they each
correspond to particular (non-overlapping) decodings of the current instruction.
If a data abort occurs at the same time as a FIQ, and FIQs are enabled (ie the CPSR’s
F flag is clear), ARM7TDMI enters the data abort handler and then immediately
proceeds to the FIQ vector. A normal return from FIQ will cause the data abort handler
to resume execution. Placing data abort at a higher priority than FIQ is necessary to
ensure that the transfer error does not escape detection. The time for this exception
entry should be added to worst-case FIQ latency calculations.
3.10 Interrupt Latencies
The worst case latency for FIQ, assuming that it is enabled, consists of the longest
time the request can take to pass through the synchroniser (
Tsyncmax
if
asynchronous), plus the time for the longest instruction to complete (
Tldm
, the longest
instruction is an LDM which loads all the registers including the PC), plus the time for
the data abort entry (
Texc
), plus the time for FIQ entry (
Tfiq
). At the end of this time
ARM7TDMI will be executing the instruction at 0x1C.
Tsyncmax
is 3 processor cycles,
Tldm
is 20 cycles,
Texc
is 3 cycles, and
Tfiq
is 2
cycles. The total time is therefore 28 processor cycles. This is just over 1.4
microseconds in a system which uses a continuous 20 MHz processor clock. The
maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has
higher priority and could delay entry into the IRQ handling routine for an arbitrary
length of time. The minimum latency for FIQ or IRQ consists of the shortest time the
request can take through the synchroniser (
Tsyncmin
) plus
Tfiq
. This is 4 processor
cycles.