Datasheet

Programmer’s Model

ARM7TDMI Data Sheet

ARM DDI 0029E

3-11

Open Access

3.9.3 Exception entry/exit summary

➲

Table 3-2: Exception entry/exit

summarises the PC value preserved in the relevant

R14 on exception entry, and the recommended instruction for exiting the exception

handler.

Notes

1 Where PC is the address of the BL/SWI/Undeﬁned Instruction fetch which had

the prefetch abort.

2 Where PC is the address of the instruction which did not get executed since

the FIQ or IRQ took priority.

3 Where PC is the address of the Load or Store instruction which generated the

data abort.

4 The value saved in R14_svc upon reset is unpredictable.

3.9.4 FIQ

The FIQ (Fast Interrupt Request) exception is designed to support a data transfer or

channel process, and in ARM state has sufﬁcient private registers to remove the need

for register saving (thus minimising the overhead of context switching).

FIQ is externally generated by taking the nFIQ input LOW. This input can except either

synchronous or asynchronous transitions, depending on the state of the ISYNC input

signal. When ISYNC is LOW, nFIQ and nIRQ are considered asynchronous, and a

cycle delay for synchronization is incurred before the interrupt can affect the processor

ﬂow.

Irrespective of whether the exception was entered from ARM or Thumb state, a FIQ

handler should leave the interrupt by executing

SUBS PC,R14_fiq,#4

Return Instruction Previous State

ARM THUMB

R14_x R14_x

Notes

BL MOV PC, R14 PC + 4 PC + 2 1

SWI MOVS PC, R14_svc PC + 4 PC + 2 1

UDEF MOVS PC, R14_und PC + 4 PC + 2 1

FIQ SUBS PC, R14_fiq, #4 PC + 4 PC + 4 2

IRQ SUBS PC, R14_irq, #4 PC + 4 PC + 4 2

PABT SUBS PC, R14_abt, #4 PC + 4 PC + 4 1

DABT SUBS PC, R14_abt, #8 PC + 8 PC + 8 3

RESET NA - - 4

Table 3-2: Exception entry/exit