Datasheet

Programmer’s Model

ARM7TDMI Data Sheet

ARM DDI 0029E

3-10

Open Access

3.9 Exceptions

Exceptions arise whenever the normal ﬂow of a program has to be halted temporarily,

for example to service an interrupt from a peripheral. Before an exception can be

handled, the current processor state must be preserved so that the original program

can resume when the handler routine has ﬁnished.

It is possible for several exceptions to arise at the same time. If this happens, they are

dealt with in a ﬁxed order - see ➲

3.9.10 Exception priorities

on page 3-14.

3.9.1 Action on entering an exception

When handling an exception, the ARM7TDMI:

1 Preserves the address of the next instruction in the appropriate Link Register.

If the exception has been entered from ARM state, then the address of the

next instruction is copied into the Link Register (that is, current PC + 4 or PC

+ 8 depending on the exception. See ➲

Table 3-2: Exception entry/exit

page 3-11 for details). If the exception has been entered from THUMB state,

then the value written into the Link Register is the current PC offset by a value

such that the program resumes from the correct place on return from the

exception. This means that the exception handler need not determine which

state the exception was entered from. For example, in the case of SWI, MOVS

PC, R14_svc will always return to the next instruction regardless of whether

the SWI was executed in ARM or THUMB state.

2 Copies the CPSR into the appropriate SPSR

3 Forces the CPSR mode bits to a value which depends on the exception

4 Forces the PC to fetch the next instruction from the relevant exception vector

It may also set the interrupt disable ﬂags to prevent otherwise unmanageable nestings

of exceptions.

If the processor is in THUMB state when an exception occurs, it will automatically

switch into ARM state when the PC is loaded with the exception vector address.

3.9.2 Action on leaving an exception

On completion, the exception handler:

1 Moves the Link Register, minus an offset where appropriate, to the PC. (The

offset will vary depending on the type of exception.)

2 Copies the SPSR back to the CPSR

3 Clears the interrupt disable ﬂags, if they were set on entry

Note

An explicit switch back to THUMB state is never needed, since restoring the CPSR

from the SPSR automatically sets the T bit to the value it held immediately prior to the

exception.