Datasheet

Programmer’s Model

ARM7TDMI Data Sheet

ARM DDI 0029E

3-6

Open Access

3.7.2 The THUMB state register set

The THUMB state register set is a subset of the ARM state set. The programmer has

direct access to eight general registers, R0-R7, as well as the Program Counter (PC),

a stack pointer register (SP), a link register (LR), and the CPSR. There are banked

Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each

privileged mode. This is shown in ➲

Figure 3-4: Register organization in THUMB state

3.7.3 The relationship between ARM and THUMB state registers

The THUMB state registers relate to the ARM state registers in the following way:

• THUMB state R0-R7 and ARM state R0-R7 are identical

• THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are

identical

• THUMB state SP maps onto ARM state R13

System & User FIQ Supervisor Abort

IRQ

Undeﬁned

CPSR CPSR

SPSR_ﬁq

CPSR

SPSR_svc

CPSR

SPSR_abt

CPSR

SPSR_irq

CPSR

SPSR_und

SP_ﬁq

LR_ﬁq

SP_svc

LR_svc

SP_abt

LR_abt

SP_irq

LR_irq

SP_und

LR_und

THUMB State General Registers and Program Counter

THUMB State Program Status Registers

= banked register