Datasheet

Signal Description
ARM7TDMI Data Sheet
ARM DDI 0029E
2-10
Open Access
SHCLKBS
Boundary scan shift clock,
phase 1
04 This control signal is provided to ease the connection of an
external boundary scan chain. SHCLKBS is used to clock the
master half of the external scan cells. When in the SHIFT-DR
state of the state machine and scan chain 3 is selected,
SHCLKBS follows TCK1. When not in the SHIFT-DR state or
when scan chain 3 is not selected, this clock is LOW. When an
external boundary scan chain is not connected, this output
should be left unconnected.
SHCLK2BS
Boundary scan shift clock,
phase 2
04 This control signal is provided to ease the connection of an
external boundary scan chain. SHCLK2BS is used to clock the
master half of the external scan cells. When in the SHIFT-DR
state of the state machine and scan chain 3 is selected,
SHCLK2BS follows TCK2. When not in the SHIFT-DR state or
when scan chain 3 is not selected, this clock is LOW. When an
external boundary scan chain is not connected, this output
should be left unconnected.
TAPSM[3:0]
TAP controller
state machine
04 This bus reflects the current state of the TAP controller state
machine, as shown in
➲ 8.4.2 The JTAG state machine on
page 8-8. These bits change off the rising edge of TCK.
TBE
Test Bus Enable.
IC When driven LOW, TBE forces the data bus D[31:0], the
Address bus A[31:0], plus LOCK, MAS[1:0], nRW, nTRANS
and nOPC to high impedance. This is as if both ABE and DBE
had both been driven LOW. However, TBE does not have an
associated scan cell and so allows external signals to be driven
high impedance during scan testing. Under normal operating
conditions, TBE should be held HIGH at all times.
TBIT O4 When HIGH, this signal denotes that the processor is executing
the THUMB instruction set. When LOW, the processor is
executing the ARM instruction set. This signal changes in phase
2 in the first execute cycle of a BX instruction.
TCK IC Test Clock.
TCK1
TCK, phase 1
04 This clock represents phase 1 of TCK. TCK1 is HIGH when TCK
is HIGH, although there is a slight phase lag due to the internal
clock non-overlap.
TCK2
TCK, phase 2
04 This clock represents phase 2 of TCK. TCK2 is HIGH when TCK
is LOW, although there is a slight phase lag due to the internal
clock non-overlap.TCK2 is the non-overlapping compliment of
TCK1.
TDI IC Test Data Input.
TDO
Test Data Output.
O4 Output from the boundary scan logic.
TMS IC Test Mode Select.
Name Type Description
Table 2-1: Signal Description (Continued)