Datasheet

Signal Description
ARM7TDMI Data Sheet
ARM DDI 0029E
2-9
Open Access
nWAIT
Not wait.
IC When accessing slow peripherals, ARM7TDMI can be made to
wait for an integer number of MCLK cycles by driving nWAIT
LOW. Internally, nWAIT is ANDed with MCLK and must only
change when MCLK is LOW. If nWAIT is not used it must be tied
HIGH.
PCLKBS
Boundary scan
update clock
04 This is a TCK2 wide pulse generated when the TAP controller
state machine is in the UPDATE-DR state and scan chain 3 is
selected. This is used by an external boundary scan chain as the
update clock. When an external boundary scan chain is not
connected, this output should be left unconnected.
RANGEOUT0
ICEbreaker Rangeout0
04 This signal indicates that ICEbreaker watchpoint register 0 has
matched the conditions currently present on the address, data
and control busses. This signal is independent of the state of the
watchpoint’s enable control bit. RANGEOUT0 changes when
ECLK is LOW.
RANGEOUT1
ICEbreaker Rangeout1
04 As RANGEOUT0 but corresponds to ICEbreaker’s watchpoint
register 1.
RSTCLKBS
Boundary Scan
Reset Clock
O This signal denotes that either the TAP controller state machine
is in the RESET state or that nTRST has been asserted. This
may be used to reset external boundary scan cells.
SCREG[3:0]
Scan Chain Register
O These 4 bits reflect the ID number of the scan chain currently
selected by the TAP controller. These bits change on the falling
edge of TCK when the TAP state machine is in the UPDATE-DR
state.
SDINBS
Boundary Scan
Serial Input Data
O This signal contains the serial data to be applied to an external
scan chain and is valid around the falling edge of TCK.
SDOUTBS
Boundary scan serial
output data
IC This control signal is provided to ease the connection of an
external boundary scan chain. This is the serial data out of the
boundary scan chain. It should be set up to the rising edge of
TCK. When an external boundary scan chain is not connected,
this input should be tied LOW.
SEQ
Sequential address.
O4 This output signal will become HIGH when the address of the
next memory cycle will be related to that of the last memory
access. The new address will either be the same as the previous
one or 4 greater in ARM state, or 2 greater in THUMB state.
The signal becomes valid during phase 1 and remains so
through phase 2 of the cycle before the cycle whose address it
anticipates. It may be used, in combination with the low-order
address lines, to indicate that the next cycle can use a fast
memory mode (for example DRAM page mode) and/or to bypass
the address translation system.
Name Type Description
Table 2-1: Signal Description (Continued)