Datasheet

Signal Description
ARM7TDMI Data Sheet
ARM DDI 0029E
2-8
Open Access
nMREQ
Not memory request.
04 This signal, when LOW, indicates that the processor requires
memory access during the following cycle. The signal becomes
valid during phase 1, remaining valid through phase 2 of the
cycle preceding that to which it refers.
nOPC
Not op-code fetch.
08 When LOW this signal indicates that the processor is fetching an
instruction from memory; when HIGH, data (if present) is being
transferred. The signal becomes valid during phase 2 of the
previous cycle, remaining valid through phase 1 of the
referenced cycle. The timing of this signal may be modified by
the use of ALE and APE in a similar way to the address, please
refer to the ALE and APE descriptions. This signal may also be
driven to a high impedance state by driving ABE LOW.
nRESET
Not reset.
IC This is a level sensitive input signal which is used to start the
processor from a known address. A LOW level will cause the
instruction being executed to terminate abnormally. When
nRESET becomes HIGH for at least one clock cycle, the
processor will re-start from address 0. nRESET must remain
LOW (and nWAIT must remain HIGH) for at least two clock
cycles. During the LOW period the processor will perform dummy
instruction fetches with the address incrementing from the point
where reset was activated. The address will overflow to zero if
nRESET is held beyond the maximum address limit.
nRW
Not read/write.
08 When HIGH this signal indicates a processor write cycle; when
LOW, a read cycle. It becomes valid during phase 2 of the cycle
before that to which it refers, and remains valid to the end of
phase 1 of the referenced cycle. The timing of this signal may be
modified by the use of ALE and APE in a similar way to the
address, please refer to the ALE and APE descriptions. This
signal may also be driven to a high impedance state by driving
ABE LOW.
nTDOEN
Not TDO Enable.
04 When LOW, this signal denotes that serial data is being driven
out on the TDO output. nTDOEN would normally be used as an
output enable for a TDO pin in a packaged part.
nTRANS
Not memory translate.
08 When this signal is LOW it indicates that the processor is in user
mode. It may be used to tell memory management hardware
when translation of the addresses should be turned on, or as an
indicator of non-user mode activity. The timing of this signal may
be modified by the use of ALE and APE in a similar way to the
address, please refer to the ALE and APE description. This
signal may also be driven to a high impedance state by driving
ABE LOW.
nTRST
Not Test Reset.
IC Active-low reset signal for the boundary scan logic. This pin must
be pulsed or driven LOW to achieve normal device operation, in
addition to the normal device reset (nRESET). For more
information, see
➲ Chapter 8, Debug Interface .
Name Type Description
Table 2-1: Signal Description (Continued)