Datasheet
Signal Description
ARM7TDMI Data Sheet
ARM DDI 0029E
2-6
Open Access
EXTERN1
External input 1.
IC This is an input to the ICEBreaker logic in the ARM7TDMI which
allows breakpoints and/or watchpoints to be dependent on an
external condition.
HIGHZ 04 This signal denotes that the HIGHZ instruction has been loaded
into the TAP controller. See
➲
Chapter 8, Debug Interface
for
details.
ICAPCLKBS
Intest capture clock
04 This is a TCK2 wide pulse generated when the TAP controller
state machine is in the CAPTURE-DR state, the current
instruction is INTEST and scan chain 3 is selected. This is used
to capture the macrocell outputs during INTEST. When an
external boundary scan chain is not connected, this output
should be left unconnected.
IR[3:0]
TAP controller Instruction
register
04 These 4 bits reflect the current instruction loaded into the TAP
controller instruction register. The instruction encoding is as
described in
➲
8.8 Public Instructions
on page 8-9. These bits
change on the falling edge of TCK when the state machine is in
the UPDATE-IR state.
ISYNC
Synchronous interrupts.
IC When LOW indicates that the nIRQ and nFIQ inputs are to be
synchronised by the ARM core. When HIGH disables this
synchronisation for inputs that are already synchronous.
LOCK
Locked operation.
08 When LOCK is HIGH, the processor is performing a “locked”
memory access, and the memory controller must wait until LOCK
goes LOW before allowing another device to access the memory.
LOCK changes while MCLK is HIGH, and remains HIGH for the
duration of the locked memory accesses. It is active only during
the data swap (SWP) instruction. The timing of this signal may be
modified by the use of ALE and APE in a similar way to the
address, please refer to the ALE and APE descriptions. This
signal may also be driven to a high impedance state by driving
ABE LOW.
MAS[1:0]
Memory Access Size.
08 These are output signals used by the processor to indicate to the
external memory system when a word transfer or a half-word or
byte length is required. The signals take the value 10 (binary) for
words, 01 for half-words and 00 for bytes. 11 is reserved. These
values are valid for both read and write cycles. The signals will
normally become valid during phase 2 of the cycle before the one
in which the transfer will take place. They will remain stable
throughout phase 1 of the transfer cycle. The timing of the
signals may be modified by the use of ALE and APE in a similar
way to the address, please refer to the ALE and APE
descriptions. The signals may also be driven to high impedance
state by driving ABE LOW.
Name Type Description
Table 2-1: Signal Description (Continued)