Datasheet

Signal Description
ARM7TDMI Data Sheet
ARM DDI 0029E
2-5
Open Access
DBGRQI
Internal debug request
04 This signal represents the debug request signal which is
presented to the processor. This is the combination of external
DBGRQ, as presented to the ARM7TDMI macrocell, and bit 1 of
the debug control register. Thus there are two conditions where
this signal can change. Firstly, when DBGRQ changes, DBGRQI
will change after a propagation delay. When bit 1 of the debug
control register has been written, this signal will change on the
falling edge of TCK when the TAP controller state machine is in
the RUN-TEST/IDLE state. See
➲ Chapter 9, ICEBreaker
Module for details.
DIN[31:0]
Data input bus
IC This is the input data bus which may be used to transfer
instructions and data between the processor and memory.This
data input bus is only used when BUSEN is HIGH. The data on
this bus is sampled by the processor at the end of phase 2 during
read cycles (i.e. when nRW is LOW).
DOUT[31:0]
Data output bus
08 This is the data out bus, used to transfer data from the processor
to the memory system. Output data only appears on this bus
when BUSEN is HIGH. At all other times, this bus is driven to
value 0x00000000. When in use, data on this bus changes
during phase 1 of store cycles (i.e. when nRW is HIGH) and
remains valid throughout phase 2.
DRIVEBS
Boundary scan
cell enable
04 This signal is used to control the multiplexers in the scan cells of
an external boundary scan chain. This signal changes in the
UPDATE-IR state when scan chain 3 is selected and either the
INTEST, EXTEST, CLAMP or CLAMPZ instruction is loaded.
When an external boundary scan chain is not connected, this
output should be left unconnected.
ECAPCLK
Extest capture clock
O This signal removes the need for the external logic in the test
chip which was required to enable the internal tristate bus during
scan testing. This need not be brought out as an external pin on
the test chip.
ECAPCLKBS
Extest capture clock for
Boundary Scan
04 This is a TCK2 wide pulse generated when the TAP controller
state machine is in the CAPTURE-DR state, the current
instruction is EXTEST and scan chain 3 is selected. This is used
to capture the macrocell outputs during EXTEST. When an
external boundary scan chain is not connected, this output
should be left unconnected.
ECLK
External clock output.
04 In normal operation, this is simply MCLK (optionally stretched
with nWAIT) exported from the core. When the core is being
debugged, this is DCLK. This allows external hardware to track
when the ARM7DM core is clocked.
EXTERN0
External input 0.
IC This is an input to the ICEBreaker logic in the ARM7TDMI which
allows breakpoints and/or watchpoints to be dependent on an
external condition.
Name Type Description
Table 2-1: Signal Description (Continued)