Datasheet

Signal Description
ARM7TDMI Data Sheet
ARM DDI 0029E
2-4
Open Access
COMMTX
Communications Channel
Transmit
O When HIGH, this signal denotes that the comms channel
transmit buffer is empty. This signal changes on the rising edge
of MCLK. See
➲ 9.11 Debug Communications Channel on
page 9-14 for more information on the debug comms channel.
CPA
Coprocessor absent.
IC A coprocessor which is capable of performing the operation that
ARM7TDMI is requesting (by asserting nCPI) should take CPA
LOW immediately. If CPA is HIGH at the end of phase 1 of the
cycle in which nCPI went LOW, ARM7TDMI will abort the
coprocessor handshake and take the undefined instruction trap.
If CPA is LOW and remains LOW, ARM7TDMI will busy-wait until
CPB is LOW and then complete the coprocessor instruction.
CPB
Coprocessor busy.
IC A coprocessor which is capable of performing the operation
which ARM7TDMI is requesting (by asserting nCPI), but cannot
commit to starting it immediately, should indicate this by driving
CPB HIGH. When the coprocessor is ready to start it should take
CPB LOW. ARM7TDMI samples CPB at the end of phase 1 of
each cycle in which nCPI is LOW.
D[31:0]
Data Bus.
IC
08
These are bidirectional signal paths which are used for data
transfers between the processor and external memory. During
read cycles (when nRW is LOW), the input data must be valid
before the end of phase 2 of the transfer cycle. During write
cycles (when nRW is HIGH), the output data will become valid
during phase 1 and remain valid throughout phase 2 of the
transfer cycle.
Note that this bus is driven at all times, irrespective of whether
BUSEN is HIGH or LOW. When D[31:0] is not being used to
connect to the memory system it must be left unconnected. See
➲ Chapter 6, Memory Interface .
DBE
Data Bus Enable.
IC This is an input signal which, when driven LOW, puts the data
bus D[31:0] into the high impedance state. This is included for
test purposes, and should be tied HIGH at all times.
DBGACK
Debug acknowledge.
04 When HIGH indicates ARM is in debug state.
DBGEN
Debug Enable.
IC This input signal allows the debug features of ARM7TDMI to be
disabled. This signal should be driven LOW when debugging is
not required.
DBGRQ
Debug request.
IC This is a level-sensitive input, which when HIGH causes
ARM7TDMI to enter debug state after executing the current
instruction. This allows external hardware to force ARM7TDMI
into the debug state, in addition to the debugging features
provided by the ICEBreaker block. See
➲ Chapter 9,
ICEBreaker Module for details.
Name Type Description
Table 2-1: Signal Description (Continued)