Datasheet

Signal Description
ARM7TDMI Data Sheet
ARM DDI 0029E
2-3
Open Access
APE
Address pipeline enable.
IC When HIGH, this signal enables the address timing pipeline. In
this state, the address bus plus MAS[1:0], nRW, nTRANS,
LOCK and nOPC change in the phase 2 prior to the memory
cycle to which they refer. When APE is LOW, these signals
change in the phase 1 of the actual cycle. Please refer to
➲
Chapter 6, Memory Interface for details of this timing.
BIGEND
Big Endian configuration.
IC When this signal is HIGH the processor treats bytes in memory
as being in Big Endian format. When it is LOW, memory is
treated as Little Endian.
BL[3:0]
Byte Latch Control.
IC These signals control when data and instructions are latched
from the external data bus. When BL[3] is HIGH, the data on
D[31:24] is latched on the falling edge of MCLK. When BL[2] is
HIGH, the data on D[23:16] is latched and so on. Please refer
to
➲ Chapter 6, Memory Interface for details on the use of
these signals.
BREAKPT
Breakpoint.
IC This signal allows external hardware to halt the execution of the
processor for debug purposes. When HIGH causes the current
memory access to be breakpointed. If the memory access is an
instruction fetch, ARM7TDMI will enter debug state if the
instruction reaches the execute stage of the ARM7TDMI pipeline.
If the memory access is for data, ARM7TDMI will enter debug
state after the current instruction completes execution.This
allows extension of the internal breakpoints provided by the
ICEBreaker module. See
➲ Chapter 9, ICEBreaker Module .
BUSDIS
Bus Disable
O This signal is HIGH when INTEST is selected on scan chain 0 or
4 and may be used to disable external logic driving onto the
bidirectional data bus during scan testing. This signal changes on
the falling edge of TCK.
BUSEN
Data bus configuration
IC This is a static configuration signal which determines whether the
bidirectional data bus, D[31:0], or the unidirectional data busses,
DIN[31:0] and DOUT[31:0], are to be used for transfer of data
between the processor and memory. Refer also to
➲ Chapter 6,
Memory Interface .
When BUSEN is LOW, the bidirectional data bus, D[31:0] is
used. In this case, DOUT[31:0] is driven to value 0x00000000,
and any data presented on DIN[31:0] is ignored.
When BUSEN is HIGH, the bidirectional data bus, D[31:0] is
ignored and must be left unconnected. Input data and
instructions are presented on the input data bus, DIN[31:0],
output data appears on DOUT[31:0].
COMMRX
Communications Channel
Receive
O When HIGH, this signal denotes that the comms channel receive
buffer is empty. This signal changes on the rising edge of MCLK.
See
➲ 9.11 Debug Communications Channel on page 9-14
for more information on the debug comms channel.
Name Type Description
Table 2-1: Signal Description (Continued)