Datasheet

Signal Description
ARM7TDMI Data Sheet
ARM DDI 0029E
2-2
Open Access
2.1 Signal Description
The following table lists and describes all the signals for the ARM7TDMI.
Transistor sizes
For a 0.6 µm ARM7TDMI:
INV4 driver has transistor sizes of p = 22.32 µm/0.6 µm
N = 12.6 µm/0.6 µm
INV8 driver has transistor sizes of p = 44.64 µm/0.6 µm
N = 25.2 µm/0.6 µm
Key to signal types
IC Input CMOS thresholds
P Power
O4 Output with INV4 driver
O8 Output with INV8 driver
Name Type Description
A[31:0]
Addresses
08 This is the processor address bus. If ALE (address latch enable)
is HIGH and APE (Address Pipeline Enable) is LOW, the
addresses become valid during phase 2 of the cycle before the
one to which they refer and remain so during phase 1 of the
referenced cycle. Their stable period may be controlled by ALE
or APE as described below.
ABE
Address bus enable
IC This is an input signal which, when LOW, puts the address bus
drivers into a high impedance state. This signal has a similar
effect on the following control signals: MAS[1:0], nRW, LOCK,
nOPC and nTRANS. ABE must be tied HIGH when there is no
system requirement to turn off the address drivers.
ABORT
Memory Abort
IC This is an input which allows the memory system to tell the
processor that a requested access is not allowed.
ALE
Address latch enable.
IC This input is used to control transparent latches on the address
outputs. Normally the addresses change during phase 2 to the
value required during the next cycle, but for direct interfacing to
ROMs they are required to be stable to the end of phase 2.
Taking ALE LOW until the end of phase 2 will ensure that this
happens. This signal has a similar effect on the following control
signals: MAS[1:0], nRW, LOCK, nOPC and nTRANS. If the
system does not require address lines to be held in this way,
ALE must be tied HIGH. The address latch is static, so ALE may
be held LOW for long periods to freeze addresses.
Table 2-1: Signal Description