PrimeCell AHB SRAM/NOR Memory Controller (PL241) ® Revision: r0p1 Technical Reference Manual Copyright © 2006 ARM Limited. All rights reserved.
PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual Copyright © 2006 ARM Limited. All rights reserved. Release Information The following changes have been made to this book. Change History Date Issue Confidentiality Change 17 March 2006 A Non-Confidential First release for r0p0. 20 December 2006 B Non-Confidential Updated for r0p1.
Contents PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual Preface About this manual .......................................................................................... x Feedback ..................................................................................................... xiv Chapter 1 Introduction 1.1 1.2 Chapter 2 Functional Overview 2.1 2.2 2.3 2.4 Chapter 3 Functional description ............................................................................
Contents Chapter 4 Programmer’s Model for Test 4.1 Chapter 5 Device Driver Requirements 5.1 Appendix A SMC integration test registers .................................................................... 4-2 Memory initialization ................................................................................... 5-2 Signal Descriptions A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 About the signals list ................................................................................... Clocks and resets .........
List of Tables PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-14 Table 2-15 Table 2-16 Table 2-17 Table 2-18 Table 2-19 Table 2-20 ARM DDI 0389B Change History ............................................................................................................. ii Static memory clocking options ..................................
List of Tables Table 2-21 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 3-13 Table 3-14 Table 3-15 Table 3-16 Table 3-17 Table 3-18 Table 3-19 Table 3-20 Table 3-21 Table 3-22 Table 3-23 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table A-1 Table A-2 Table A-3 Table A-4 Table A-5 Table A-6 Table A-7 vi Synchronous read and asynchronous write opmode chip register settings ............ 2-37 Register summary .....................
List of Figures PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual Figure 1-1 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 2-8 Figure 2-9 Figure 2-10 Figure 2-11 Figure 2-12 Figure 2-13 Figure 2-14 Figure 2-15 Figure 2-16 Figure 2-17 Figure 2-18 Figure 2-19 ARM DDI 0389B Key to timing diagram conventions ............................................................................. xii AHB MC (PL241) configuration ............................
List of Figures Figure 2-20 Figure 2-21 Figure 2-22 Figure 2-23 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-17 Figure 3-18 Figure 3-19 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 5-1 Figure 5-2 Figure 5-3 Figure A-1 viii Synchronous burst read in multiplexed-mode ........................................................ 2-34 Synchronous burst write ....
Preface This preface introduces the PrimeCell AHB SRAM/NOR Memory Controller (MC) (PL241) Technical Reference Manual. It contains the following sections: • About this manual on page x • Feedback on page xiv. ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved.
Preface About this manual This is the Technical Reference Manual (TRM) for the PrimeCell AHB SRAM/NOR Memory Controller. Product revision status The rnpn identifier indicates the revision status of the product described in this manual, where: rn Identifies the major revision of the product. pn Identifies the minor revision or modification status of the product.
Preface Appendix A Signal Descriptions Read this appendix for a description of the AHB MC input and output signals. Glossary Read the Glossary for definitions of terms used in this manual. Conventions Conventions that this manual can use are described in: • Typographical • Timing diagrams on page xii • Signals on page xii • Numbering on page xiii.
Preface Note Angle brackets can also enclose a permitted range of values. The example, <0-3>, shows that in name extensions, only one of the values 0, 1, 2, or 3 is valid. Timing diagrams The figure named Key to timing diagram conventions explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Preface Prefix B Denotes AXI write response channel signals. Prefix C Denotes AXI low-power interface signals. Prefix H Denotes Advanced High-performance Bus (AHB) signals. Prefix P Denotes Advanced Peripheral Bus (APB) signals. Prefix R Denotes AXI read data channel signals. Prefix W Denotes AXI write data channel signals. Numbering The Verilog numbering convention is: ' This is a Verilog method of abbreviating constant numbers.
Preface Feedback ARM Limited welcomes feedback on the AHB MC and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier giving: • the product name • a concise explanation of your comments. Feedback on this manual If you have any comments on this manual, send email to errata@arm.com giving: • the title • the number • the relevant page number(s) to which your comments apply • a concise explanation of your comments.
Chapter 1 Introduction This chapter introduces the AHB MC. It contains the following sections: • About the AHB MC on page 1-2 • Supported devices on page 1-5. ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved.
Introduction 1.1 About the AHB MC The AHB MC is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral. It is developed, tested, and licensed by ARM Limited. The AHB MC takes advantage of the newly developed Static Memory Controller (SMC). The AHB MC has an AHB port with access to the external memory. The AHB port has a bridge interface to the memory controller. There is a separate AHB port to configure the memory controller.
Introduction 1.1.1 AHB interface The interface converts the incoming AHB transfers to the protocol used internally by the AHB MC.
Introduction 1.1.3 SMC The SMC is a high-performance, area-optimized SRAM memory controller. The SMC is pre-configured and validated for: • the SRAM memory type • the number of SRAM memory devices • the maximum SRAM memory width. The SRAM memory interface type is defined as supporting: • synchronous or asynchronous SRAM • Pseudo Static Random Access Memory (PSRAM) • NOR flash • NAND flash devices with an SRAM interface.
Introduction 1.2 Supported devices The SMC supports SRAM/NOR, see SMC on page 1-4. The Release Note provides a specific list of memory devices tested with each configuration. Some memory devices or series of memory devices have specific requirements: Intel W18 series NOR FLASH, for example 28f128W18td These devices, when in synchronous operation, use a WAIT pin. However non-array operations when in synchronous mode do not use the WAIT pin and it is always asserted.
Introduction 1-6 Copyright © 2006 ARM Limited. All rights reserved.
Chapter 2 Functional Overview This chapter describes the major components of the AHB MC and how they operate. It contains the following sections: • Functional description on page 2-2 • SMC on page 2-4 • Functional operation on page 2-7. • SMC functional operation on page 2-15. ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved.
Functional Overview 2.1 Functional description Figure 2-1 shows an AHB MC (PL241) configuration. $+% 0& 3/ $+% LQWHUIDFH $+% 0 6 60& $+% FRQILJXUDWLRQ SRUW $+% WR $3% EULGJH 0 ELW 65$0 125 IRXU FKLSV $3% 6 Figure 2-1 AHB MC (PL241) configuration This section is divided into: • AHB interface • AHB to APB bridge • Clock domains on page 2-3 • Low-power interface on page 2-3 • SMC on page 2-4. 2.1.1 AHB interface The AHB MC fully supports the AMBA AHB 2.0 specification.
Functional Overview 2.1.3 Clock domains The memory controller has two clock domains: AHB clock domain This is clocked by hclk, smc_aclk and reset by hresetn. Static memory clock domain This is clocked by smc_mclk0, smc_mclk0n and reset by smc_mreset0n. Figure 2-2 shows the two clock domains.
Functional Overview 2.2 SMC Figure 2-3 shows a block diagram of the SMC.
Functional Overview 2.2.1 SMC interface The SMC interface processes the incoming AHB transfers and sends them to the command format block. 2.2.2 APB slave interface The SMC has 4KB of memory allocated to it. The APB slave interface accesses the SMC registers to program the memory system configuration parameters and to provide status information. See Chapter 3 Programmer’s Model and APB slave interface operation on page 2-19 for more information. 2.2.
Functional Overview 2.2.6 Pad interface The pad interface module provides a registered I/O interface for data and control signals. It also contains interrupt generation logic. Figure 2-4 shows the SRAM pad interface external signals. Clock and reset signals are omitted.
Functional Overview 2.3 Functional operation This section is divided into: • AHB interface operation • AHB to APB bridge operation on page 2-10 • Clock domain operation on page 2-11 • Low-power interface operation on page 2-12 • SMC functional operation on page 2-15. 2.3.
Functional Overview Undefined length INCR bursts All undefined length INCR bursts are converted to INCR bursts of length four. Many AHB masters rely on using undefined length INCR bursts to access data. If each INCR transfer is processed as a single transfer by the internal protocol then the performance is significantly degraded. The bridge converts the incoming INCR transfers to INCR transfers of length four, INCR4.
Functional Overview If transfers are described as non-bufferable then the bridge must wait for the write response to indicate that the transfer has been completed to memory. If numerous bufferable writes are performed, followed by a non-bufferable write, then the bridge must wait until it receives the write response associated with the final write. Read after write hazard detection buffer A RAW hazard detection buffer avoids potential RAW hazards.
Functional Overview Registered HWDATA The interconnect used within the AHB MC contains combinatorial paths for the write data. To improve the synthesis timing, HWDATA is registered and makes these paths internal to the design. Big-endian 32-bit mode The AHB MC supports the option of storing data to memory in big-endian 32-bit mode. Each bridge contains the logic to implement this data mapping depending on the big_endian input tie-off.
Functional Overview [)))) 5HDG DV ]HUR [ 60& FRQILJ [ 5HVHUYHG [ $+%& PHPRU\ PDS Figure 2-6 AHBC memory map The other fourteen 4KB regions are read as zero. The lower 16 bits of the AHB address decode the memory controller that is being used. An external AHB decoder determines where in the system memory map, this 64KB region is located. See About the programmer’s model on page 3-2 for information on the internal memory controller configuration registers.
Functional Overview Static memory clocking options Table 2-1 lists the static memory clocking options.
Functional Overview an active output _cactive Where: is ahb or smc. Figure 2-7 explains the protocol for the interface by showing a request to enter low-power mode. 7 7 7 7 7 KFON DKEBFV\VUHT DKEBFV\VDFN DKEBFDFWLYH Figure 2-7 Request to enter low-power mode The memory controller receives a request to enter low-power mode, indicated by _csysreq being driven LOW by the system clock controller, as shown at T1.
Functional Overview The AHB domain accepts or denies requests based on whether it is busy performing any transfers. Figure 2-9 shows that static memory controllers always accept requests after they have performed the required operations to prepare the external memory for the clock to be switched off. 7 7 7 7 7 VPFBDFON VPFBFV\VUHT VPFBFV\VDFN VPFBFDFWLYH Figure 2-9 Accepting requests The low-power request smc_csysreq is driven LOW at time T1.
Functional Overview 2.4 SMC functional operation This section describes: • Operating states • Clocking and resets on page 2-16 • Miscellaneous signals on page 2-18 • APB slave interface operation on page 2-19 • Format block on page 2-19 • Memory manager operation on page 2-22 • Interrupts operation on page 2-27 • Memory interface operation on page 2-27. 2.4.1 Operating states The operation of the SMC is based on three operating states. In this section, each state is described.
Functional Overview The state transitions are: Ready to Reset When reset is asserted to the smc_aclk domain, it enters the Reset state. Reset to Ready When reset is deasserted to the smc_aclk domain, it enters the Ready state. Ready to Low-power The Low-power state is entered when the SMC next becomes idle after either: • the SMC receives a low-power request through the APB smc_memc_cfg_set Register • the SMC receives a low-power request through the SMC low-power interface.
Functional Overview These clocks can be grouped into two clock domains: AHB domain smc_aclk is in this domain. You can only stop the smc_aclk domain signals when the SMC is in low-power mode. Memory clock domain The smc_mclk0 and smc_mclk0n are in this domain. smc_mclk0n is an inverted version of smc_mclk0. smc_mclk0 is used for timing and control signals.
Functional Overview You can change both reset signals asynchronously to their respective clock domain. Internally to the SMC the deassertion of the hresetn signal is synchronized to smc_aclk. The deassertion of smc_mreset0n is synchronized internally to smc_mclk0 and smc_mclk0n. 2.4.
Functional Overview smc_msync0 When HIGH, indicates smc_mclk0 is synchronous to smc_aclk. Otherwise they are asynchronous. Ensure that smc_msync0 is tied to the same value as smc_async0. smc_rst_bypass Use this signal for ATPG testing only. Tie it LOW for normal operation. smc_use_ebi When HIGH, indicates that the SMC must operate with a PrimeCell EBI. See the ARM PrimeCell External Bus Interface (PL220) Technical Reference Manual. 2.4.
Functional Overview The SMC ensures the ordering of read transfers from a single port is maintained RAR, and additionally that the ordering of write transfers from a single master is maintained WAW. SRAM memory accesses This section describes: • Standard SRAM access • Memory address shifting • Memory burst alignment • Memory burst length on page 2-21 • Booting using the SRAM on page 2-21. Standard SRAM access The programmer’s view is a flat area of memory.
Functional Overview memory bursts, terminating a memory transfer at the burst boundary. Also ensure the page size is an integer multiple of the burst length, to avoid a memory burst crossing a page boundary. When the burst_align bit is not set, the SMC ignores the memory burst boundary when mapping commands onto memory commands. This setting is intended for use with devices such as NOR flash. These devices have no concept of pages.
Functional Overview 2.4.6 Memory manager operation The memory manager module is responsible for controlling the state of the SMC and the updating of chip configuration registers. This subsection describes: • Low-power operation • Chip configuration registers • Direct commands on page 2-24. Low-power operation The SMC accepts requests to enter the Low-power state through either the SMC low-power interface or the APB register interface.
Functional Overview The APB registers smc_set_cycles and smc_set_opmode act as holding registers, the configuration registers within the manager are only updated if either: • the smc_direct_cmd Register indicates only a register update is taking place • the smc_direct_cmd Register indicates either a modereg operation or an memory access has taken place, and is complete. The chip configuration registers are available as read only registers in the address map of the APB interface.
Functional Overview Direct commands The SMC enables code to be executed from the memory while simultaneously, from the software perspective, moving the same chip to a different operating mode. This is achieved by synchronizing the update of the chip configuration registers from the holding registers with the dispatch of the memory configuration register write. The SMC provides two mechanisms for simultaneously updating the controller and memory configuration registers.
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Functional Overview 6WDUW $ :ULWH WLPLQJ SDUDPHWHUV DQG RSHUDWLQJ PRGH WR WKH PHPRU\ FRQWUROOHU KROGLQJ UHJLVWHUV :ULWH UHTXLUHG H[WHUQDO FKLS VHOHFW QXPEHU DQG UHTXLUHG PRGH UHJLVWHU YDOXH WR WKH 'LUHFW &RPPDQG 5HJLVWHU 7KH PHPRU\ FRQWUROOHU GHWHFWV WKH DFN VLJQDO DQG XSGDWHV WKH PRGH DQG WLPLQJ UHJLVWHUV RI WKH UHOHYDQW FKLS VHOHFW DQG QHJDWHV UHT 7KH PHPRU\ LQWHUIDFH GHWHFWV WKH QHJDWLRQ RI UHT FOHDUV DFN DQG UH HQDEOHV DFFHVVHV WR WKH XSGDWHG FKLS VHOHFW PHPRU\ (QG 7KH PHPRU\ FRQWUR
Functional Overview 2.4.7 Interrupts operation The next read to any chip select on the appropriate memory interface clears the interrupt. The interrupt outputs are generated through a combinational path from the relevant input pin. This enables you to place the SMC in Low-power state, and to stop the clocks while waiting for an interrupt. When interrupts are disabled, a synchronized version of the interrupt input is still readable through the APB interface. 2.4.
Functional Overview Read data output by the memory device is also registered on the rising edge of smc_mclk0n, equivalent to the falling edge of smc_mclk0, for asynchronous reads. For synchronous reads, read data is registered using the fed back clock, smc_fbclk_in. For synchronous and asynchronous accesses, the data is then pushed onto the read data FIFO to be returned by the SMC interface.
Functional Overview VPFBPFON W5& VPFBFVBQB > @ VPFBRHBQB W&(2( VPFBDGGB > @ $ ' VPFBGDWDBLQB > @ ' UHDGBGDWD Figure 2-14 Asynchronous read Asynchronous read in multiplexed-mode Table 2-4 and Table 2-5 list the smc_opmode0_<0-3> and SRAM Register settings.
Functional Overview Note In multiplexed-mode, both address and data are output by the SMC on the smc_data_out_0[31:0] output bus. Read data is accepted on the smc_data_in_0[31:0] bus. Asynchronous write Table 2-6 and Table 2-7 list the smc_opmode0_<0-3> and SRAM Register settings.
Functional Overview Asynchronous write in multiplexed-mode Table 2-8 and Table 2-9 list the smc_opmode0_<0-3> and SRAM Register settings.
Functional Overview Figure 2-18 shows a page read access, with an initial access time, tRC, of three cycles, an output enable assertion delay, tCEOE, of two cycles and a page access time, tPC, of one cycle. Page mode is enabled in the SMC by setting the opmode Register for the relevant chip to asynchronous reads and the burst length to the page size. Note Multiplexed-mode page accesses are not supported.
Functional Overview Figure 2-19 shows a burst read with the smc_wait_0 output of the memory used to delay the transfer. • • Note Synchronous memories have a configuration register enabling smc_wait_0 to be asserted either on the same clock cycle as the delayed data or a cycle earlier. The SMC only supports smc_wait_0 being asserted one cycle early, enabling smc_wait_0 to be initially sampled with the fed back clock and then with smc_mclk0 before being used by the FSM.
Functional Overview Synchronous burst read in multiplexed-mode Table 2-14 and Table 2-15 list the smc_opmode0_<0-3> and SRAM Register settings.
Functional Overview Synchronous burst write Table 2-16 and Table 2-17 list the smc_opmode0_<0-3> and SRAM Register settings.
Functional Overview Synchronous burst write in multiplexed-mode Table 2-18 and Table 2-19 list the smc_opmode0_<0-3> and SRAM Register settings.
Functional Overview Synchronous read and asynchronous write Table 2-20 and Table 2-21 list the smc_opmode0_<0-3> and SRAM Register settings.
Functional Overview VPFBPFON VPFBFONBRXWB > @ VPFBIEFONBLQB $''5 $ VPFBDGGB > @ $''5 % VPFBFVBQB > @ W75 VPFBDGYBQB VPFBRHBQB VPFBZHBQB GDWD ' % ' $ ' $ ' $ ' $ VPFBGDWDBHQB GDWD UHDGBGDWD ' $ ' $ ' $ ' $ Figure 2-23 Synchronous read and asynchronous write Programming tRC and tWC when the controller operates in synchronous mode For tRC: • when using memory devices that are not wait-enabled, you must program tRC to be the number of clock cycles required before valid data
Functional Overview For tWC: • when using memory devices that are not wait-enabled, you must program tWC to be the number of clock cycles required before the first data is written, following the assertion of cs_n • when using memory devices that are wait-enabled, you must program tWC to be the number of clock cycles required before wait is active and stable, following the assertion of cs_n.
Functional Overview 2-40 Copyright © 2006 ARM Limited. All rights reserved.
Chapter 3 Programmer’s Model This chapter describes the registers of the SMC and provides information for programming the device. It contains the following sections: • About the programmer’s model on page 3-2 • Register summary on page 3-3 • Register descriptions on page 3-6. ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved.
Programmer’s Model 3.1 About the programmer’s model The SMC has 4KB of memory allocated to it from a base address of 0x1000 to a maximum address of 0x1FFF. Figure 3-1 shows that the register map address range is split into the following regions: SMC configuration registers Use these registers for the global configuration, and control of operating state, of the SMC. SMC chip select configuration registers These registers hold the operating parameters of each chip select.
Programmer’s Model 3.2 Register summary Figure 3-2 shows the SMC configuration register map.
Programmer’s Model Note Figure 3-3 on page 3-3 shows the maximum number of supported chips. If you intend to use fewer, then the highest chip configuration blocks of the correct type are read back as zero. Figure 3-4 shows the SMC user configuration memory register map. VPFBXVHUBFRQILJ VPFBXVHUBVWDWXV [ [ Figure 3-4 SMC user configuration register map Figure 3-5 shows the SMC peripheral and PrimeCell configuration register map.
Programmer’s Model Table 3-1 Register summary (continued) Name Base offset Type Reset value Description smc_set_cycles 0x1014 WO N/A See SMC Set Cycles Register at 0x1014 on page 3-11. smc_set_opmode 0x1018 WO N/A See SMC Set Opmode Register at 0x1018 on page 3-12. smc_refresh_period_0 0x1020 R/W 0x00000000 See SMC Refresh Period 0 Register at 0x1020 on page 3-15.
Programmer’s Model 3.3 Register descriptions This section describes the SMC registers. 3.3.1 SMC Memory Controller Status Register at 0x1000 The read-only smc_memc_status Register provides information on the configuration of the SMC and also the current state of the SMC. This register cannot be read in the Reset state. Figure 3-6 shows the register bit assignments.
Programmer’s Model 3.3.2 SMC Memory Interface Configuration Register at 0x1004 The read-only smc_memif_cfg Register provides information on the configuration of the memory interface. This register cannot be read in the Reset state. Figure 3-7 shows the register bit assignments.
Programmer’s Model Table 3-3 smc_memif_cfg Register bit assignments (continued) Bits Name Function [3:2] memory_chips0 Returns the number of different chip selects that the memory interface 0 supports: b00 = 1 chip b01 = 2 chips b10 = 3 chips b11 = 4 chips. [1:0] memory_type0 Returns the memory interface 0 type: b00 = reserved b01 = SRAM b10 = NAND b11 = reserved. 3.3.
Programmer’s Model Table 3-4 lists the register bit assignments. Table 3-4 smc_memc_cfg_set Register bit assignments 3.3.4 Bits Name Function [31:3] - Reserved, undefined. Write as zero. [2] low_power_req b0 = no effect b1 = request the SMC to enter Low-power state when it next becomes idle. [1] - Reserved, undefined. Write as zero. [0] int_enable0 b0 = no effect b1 = interrupt enable, memory interface 0.
Programmer’s Model 3.3.5 SMC Direct Command Register at 0x1010 The write-only smc_direct_cmd Register passes commands to the external memory, and controls the updating of the chip configuration registers with values held in the set_opmode and set_cycles registers. This register cannot be written to in either the Reset or Low-power state. Figure 3-10 shows the register bit assignments.
Programmer’s Model 3.3.6 SMC Set Cycles Register at 0x1014 This is the holding register for the smc_set_cycles0_. The write-only smc_set_cycles Register enables the time interval to be set for holding registers before data can be written to the memory manager specific registers. This register cannot be written to in either the Reset or Low-power state. Figure 3-11 shows the register bit assignments.
Programmer’s Model 3.3.7 SMC Set Opmode Register at 0x1018 This register is the holding register for the smc_opmode0_ working registers. The write-only smc_set_opmode Register cannot be written to in either the Reset or Low-power state. Figure 3-12 shows the register bit assignments. Note Table 3-8 on page 3-13 describes register holding, see Memory manager operation on page 2-22 for more information.
Programmer’s Model Table 3-8 lists the register bit assignments. Table 3-8 smc_set_opmode Register bit assignments Bits Name Function [31:16] - Reserved, undefined, write as zero. [15:13] set_burst_align Holding register for value to be written to the specific SRAM chip opmode Register burst_align field.
Programmer’s Model Table 3-8 smc_set_opmode Register bit assignments (continued) Bits Name Function [9:7] set_wr_bl Holding register for value to be written to the specific SRAM chip smc_opmode Register bls field. Encodes the memory burst length: b000 = 1 beat b001 = 4 beats b010 = 8 beats b011 = 16 beats b100 = 32 beats b101 = continuous b110-b111 = reserved. [6] set_wr_sync Holding register for value to be written to the specific SRAM chip smc_opmode Register wr_sync field.
Programmer’s Model 3.3.8 SMC Refresh Period 0 Register at 0x1020 The read/write smc_refresh_period_0 Register enables the AHB MC to perform refresh cycles for PSRAM devices that you connect to memory interface 0. You cannot access this register in either the Reset or low-power states. Figure 3-13 shows the register bit assignments. 8QGHILQHG SHULRG Figure 3-13 smc_refresh_period_0 Register bit assignments Table 3-9 lists the register bit assignments.
Programmer’s Model Table 3-10 lists the register bit assignments. Table 3-10 smc_sram_cycles Register bit assignments 3.3.
Programmer’s Model Table 3-11 lists the register bit assignments. Table 3-11 smc_opmode Register bit assignments Bits Name Function [31:24] address_match Returns the value of this tie-off. This is the comparison value for address bits [31:24] to determine the chip that is selected. [23:16] address_mask Returns the value of this tie-off. This is the mask for address bits[31:24] to determine the chip that must be selected. A logic 1 indicates the bit is used for comparison.
Programmer’s Model Table 3-11 smc_opmode Register bit assignments (continued) Bits Name Function [6] wr_sync When set, the memory operates in write sync mode. [5:3] rd_bl Determines the memory burst lengths for reads: b000 = 1 beat b001 = 4 beats b010 = 8 beats b011 = 16 beats b100 = 32 beats b101 = continuous b110-b111 = reserved. [2] rd_sync When set, the memory operates in read sync mode.
Programmer’s Model 3.3.12 SMC User Configuration Register at 0x1204 The smc_user_config Register is a general purpose write-only register. This register sets the value of the smc_user_config[7:0] primary outputs. The smc_user_config Register can be written in all states. Figure 3-17 shows the register bit assignments. 8QGHILQHG VPFBXVHUBFRQILJ Figure 3-17 smc_user_config Register bit assignments Table 3-13 lists the register bit assignments.
Programmer’s Model Figure 3-18 shows the correspondence between bits of the smc_ periph_id registers and the conceptual 32-bit Peripheral ID Register.
Programmer’s Model SMC Peripheral Identification Register 1 The smc_periph_id_1 Register is hard-coded and the fields within the register indicate the value. Table 3-16 lists the register bit assignments.
Programmer’s Model 3.3.14 SMC PrimeCell Identification Registers <0-3> at 0x1FF0-0x1FFC The smc_pcell_id Registers are four 8-bit wide registers, that span address locations 0xFF0-0FFC. The registers can conceptually be treated as a single register that holds a 32-bit PrimeCell ID value. You can use the register for automatic BIOS configuration. The smc_pcell_id Register is set to 0xB105F00D. The register can be accessed with one wait state. Table 3-19 lists the register bit assignments.
Programmer’s Model The following sections describe the smc_pcell_id Registers: • SMC PrimeCell Identification Register 0 • SMC PrimeCell Identification Register 1 • SMC PrimeCell Identification Register 2 on page 3-24 • SMC PrimeCell Identification Register 3 on page 3-24. Note These registers cannot be read in the Reset state. SMC PrimeCell Identification Register 0 The smc_pcell_id_0 Register is hard-coded and the fields within the register indicate the value.
Programmer’s Model SMC PrimeCell Identification Register 2 The smc_pcell_id_2 Register is hard-coded and the fields within the register indicate the value. Table 3-22 lists the register bit assignments. Table 3-22 smc_pcell_id_2 Register bit assignments Bits Name Function [31:8] - Reserved, read undefined [7:0] smc_pcell_id_2 These bits read back as 0x5 SMC PrimeCell Identification Register 3 The smc_pcell_id_3 Register is hard-coded and the fields within the register indicate the value.
Chapter 4 Programmer’s Model for Test This chapter describes the additional logic for functional verification and production testing. It contains the following section: • SMC integration test registers on page 4-2. ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved.
Programmer’s Model for Test 4.1 SMC integration test registers Test registers are provided for integration testing. Figure 4-1 shows the SMC integration test register map. VPFBLQWBRXWSXWV VPFBLQWBLQSXWV VPFBLQWBFIJ [ ( [ ( [ ( Figure 4-1 SMC integration test register map Table 4-1 lists the SMC integration test registers. Table 4-1 SMC test register summary 4.1.
Programmer’s Model for Test Table 4-2 lists the register bit assignments. Table 4-2 smc_int_cfg Register bit assignments Bits Name Function [31:1] Undefined Read undefined. Write as zero. [0] int_test_en When set, outputs are driven from the integration test registers and tied-off, and inputs can change for integration testing. 4.1.2 Integration Inputs Register at 0x1E04 The read-only smc_int_inputs Register enables an external master to access the inputs of the SMC using the APB interface.
Programmer’s Model for Test Table 4-3 smc_int_inputs Register bit assignments (continued) 4.1.3 Bits Name Function [2] smc_ebignt0 Returns the value of the smc_ebigrant0 input [1] smc_use_ebi Returns the value of the smc_use_ebi input [0] smc_csysreq Returns value of this external input Integration Outputs Register at 0x1E08 The write-only smc_int_outputs Register enables an external master to access the outputs of the SMC using the APB interface.
Chapter 5 Device Driver Requirements This chapter contains various flow diagrams to aid in the development of a software driver for the SMC. It contains the following section: • Memory initialization on page 5-2. ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved.
Device Driver Requirements 5.1 Memory initialization Figure 5-1 on page 5-3 and Figure 5-3 on page 5-5 shows the sequence of events that a device driver must carry out to initialize the memory controller and a memory device to ensure the configuration of both is synchronized. Typically, PSRAM devices can have the mode register programmed using the address bus only.
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Device Driver Requirements 5-6 Copyright © 2006 ARM Limited. All rights reserved.
Appendix A Signal Descriptions This appendix lists and describes the processor signals. It contains the following sections: • About the signals list on page A-2 • Clocks and resets on page A-3 • AHB signals on page A-4 • SMC memory interface signals on page A-5 • SMC miscellaneous signals on page A-6 • Low-power interface on page A-7 • Configuration signal on page A-8 • Scan chains on page A-9. ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved.
Signal Descriptions A.1 About the signals list This appendix lists the PL241 signals. Figure A-1 shows how the signals are grouped. $+% 0& 3/ 6WDWLF PHPRU\ LQWHUIDFH &ORFNV DQG UHVHWV $+% 60& WLH RIIV $+%& /RZ SRZHU LQWHUIDFH &RQILJXUDWLRQ VLJQDOV Figure A-1 AHB MC PL241 grouping of signals where: AHBC = AHB Configuration signals A-2 Copyright © 2006 ARM Limited. All rights reserved.
Signal Descriptions A.2 Clocks and resets Table A-1 lists the clock and reset signals.
Signal Descriptions A.3 AHB signals Table A-2 lists the AHB signals.
Signal Descriptions A.4 SMC memory interface signals Table A-3 lists the SMC memory interface signals.
Signal Descriptions A.5 SMC miscellaneous signals Table A-4 lists the SMC miscellaneous signals.
Signal Descriptions A.6 Low-power interface Table A-5 lists the low-power interface signals.
Signal Descriptions A.7 Configuration signal Table A-6 lists the configuration signal. Table A-6 Configuration signal A-8 Name Type Source/ destination Description big_endian Input Tie-off Big-endian mode configuration tie-off Copyright © 2006 ARM Limited. All rights reserved.
Signal Descriptions A.8 Scan chains Table A-7 lists the scan chain signals.
Signal Descriptions A-10 Copyright © 2006 ARM Limited. All rights reserved.
Glossary This glossary describes some of the terms used in technical documents from ARM Limited. Advanced High-performance Bus (AHB) A bus protocol with a fixed pipeline between address/control and data phases. It only supports a subset of the functionality provided by the AMBA AXI protocol. The full AMBA AHB protocol specification includes a number of features that are not commonly required for master and slave IP developments and ARM Limited recommends only a subset of the protocol is usually used.
Glossary Advanced Peripheral Bus (APB) A simpler bus protocol than AHB. It is designed for use with ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. Connection to the main system bus is through a system-to-peripheral bus bridge that helps to reduce system power consumption. AHB See Advanced High-performance Bus. Aligned A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned.
Glossary Boundary scan chain A boundary scan chain is made up of serially-connected devices that implement boundary scan technology using a standard JTAG TAP interface. Each device contains at least one TAP controller containing shift registers that form the chain connected between TDI and TDO, through which test data is shifted. Processors can contain several shift registers to enable you to access selected parts of the device. Burst A group of transfers to consecutive addresses.
Glossary SBO See Should Be One. SBZ See Should Be Zero. SBZP See Should Be Zero or Preserved. Scan chain A scan chain is made up of serially-connected devices that implement boundary scan technology using a standard JTAG TAP interface. Each device contains at least one TAP controller containing shift registers that form the chain connected between TDI and TDO, through which test data is shifted. Processors can contain several shift registers to enable you to access selected parts of the device.
Glossary Remapping Changing the address of physical memory or devices after the application has started executing. This is typically done to permit RAM to replace ROM when the initialization has been completed. Reserved A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces Unpredictable results if the contents of the field are not zero.
Glossary Glossary-6 Copyright © 2006 ARM Limited. All rights reserved.
