User manual

18: Watchdog Timer
GP4020 GPS Baseband Processor Design Manual 179
All Watchdog Registers are 32-bits wide.
18.3.1
Watchdog Control / Status Register - CONSTAT - Memory Offset 0x000
The control register is 32-bits wide, with unused bits defined as zero. Attempts to access the register as a byte or a
half-word will cause a bus error exception.
Bit
No.
Mnemonic Description Reset
Value
R/W
31:20
Reserved
0-
19 EN Mask that controls whether the zero count state of the watchdog generates an
interrupt to the ARM7TDMI processor.
'1' = Generate interrupt
'0' = Mask Disabled
0R/W
18 OVF Read-only: Overflow - set whenever the watchdog time-out (secondary) counter
reaches zero. OVF can only be reset by restarting the watchdog timer.
0R
17
Reserved
0-
16 RUN Read-only: Run Status - indicates whether the Watchdog counters are enabled
and running at the moment of access.
'1' = Watchdog running
'0' = Watchdog NOT running
0R
15:8
Reserved
0x00 -
7:0 TIME_DELAY Time-out delay used by secondary (Time-out) counter. Value equates to number
of (UART_CLK/16) cycles required in the delay. The secondary counter counts
down from this value to zero and then generates a system reset unless the
WDOG is re-started.
Most Significant Bit: Bit 7
0xFF R/W
Table 18.2 Watchdog CONSTAT Register
18.3.2
Watchdog Primary Counter Reload Register - RELOAD - Memory Offset 0x004
The PR_RELOAD value is loaded into the Primary Interrupt Counter each time the RESTART Key
(=0xECD9F7BD) is sent to the RESTART register. It signifies the time interval between WATCH_INT interrupt
events:
Watchdog Interrupt period = PR_RELOAD / UART_CLK frequency
Bit
No.
Mnemonic Description Reset Value R/W
31: 0
PR_RELOAD
The WDOG primary counter is reloaded with this value following a
WDOG re-start or a system reset. After reloading the WDOG counts
from this value down towards zero.
0xFFFFFFFF R/W
Table 18.3 Watchdog RELOAD Register
18.3.3
Watchdog Primary Counter Read Register - READ - Memory Offset 0x008
Bit
No.
Mnemonic Description Reset Value R/W
31: 0
PC_READ
Current primary counter read value.
Accessible in TEST mode only.
0xFFFFFFFF R
Table 18.4 Watchdog READ Register