User manual

15: 1PPS Timemark Generator
150 GP4020 GPS Baseband Processor Design Manual
TIC
GENERATOR
(Count down
to Zero)
Clock
divide
by 7
LOAD ZERO
1ms
delay
TIC
ARM_TIMEMARK
Modulo 7 Add
TIC_CORR[2:0]
Phase_offset
Overflow
TIMEMARK / TIC
Overflow
control
TIC_INT
Timemark
Delay
STORE
PHASE
OFFSET
TIC_INT[1:0]
22 Bit
Down Counter
TIM_DEL[21:16]
TIM_DEL[15:0]
TIM_DEL_ENAB
TIM_DEL
22bit Register
LOAD
TIM_DEL_CLK
TIM_DEL_ENAB
RELOAD_TIC
RAW_TIMEMARKM_CLK
PER_STAT
[15:14]
TIC_INT[1:0]
TIC_RET[15:0]
PHASE_OFF[2:0]
TIC
ADJ_TIC
ADJ_TIC TIC_CORR[2:0]
TIC_TIME
PHASE_OFF[2:0]
TIC_TIME
RETEN[7:0]
RETENTION
REGISTER
TIM_DEL_LO
[15:0]
TIM_DEL[15:0]
TIM_DEL_HI
[7:0]
TIM_DEL[21:16]
40,000
CLEAR SET
0
5 bit
Down
Counter
FREE_RUN_RATIO[4:0]
0
1ms
delay
FREE_RUN_TIMEMARK
M_CLK
(from SYSTEM
CLOCK
GENERATOR)
40MHz
5.71MHz
1PPS
TIMEMARK
GENERATOR
12 CHANNEL
CORRELATOR
UIM BUS
UIM BUS
PROG_TIC
_LOW[15:0]
TIMEMARK
_CONTROL[6:0]
PROG_TIC
_HIGH[4:0]
ARM_TIMEMARK FREE_RUN_TIMEMARK FREE_RUN_RATIO[4:0]
UIM BUS
TIC (to PCL)
TIMEMARK (to PCL)
Load
M_CLK
RAW_TIMEMARK
TIC
RAW TIMEMARK
GENERATOR
TIC PERIOD
SLEW LOGIC
TIMEMARK DELAY
COUNTER LOGIC
TIC_RET[15:8]
NPOR_RESET
(FROM PCL)
UIM ADDRESS & DATA BUS
NOTE: TIC_RET[15:8]
is NOT RESET by
NPOR_RESET
Figure 15.1 1PPS Timemark Generator, with interface to 12-channel correlator block