User manual

1: Introduction
8 GP4020 GPS Baseband Processor Design Manual
1.4 Typical Application
ANTENNA
470 470
1k
SAMPCLK SIGN0 MAG0
(58) (59) (61) (62) (63) (64) (56)
GP4020
(84)
BuILD
_CLK
M_CLK
POWER_GOOD RF_PLL_LOCK SAMPCLK
SIGN0
MAG0 CLK_I CLK_T
BOOT ROM
SRAM
(2K X 32)
FIREFLY MF1
MICROCONTROLLER
UART 1
ARM7TDMI
FLASH
EPROM
(16-BIT)
STATIC
RAM
(16-BIT)
1PPS
GENERATOR
WATCHDOG
BSIO 3-WIRE
SERIAL
INTERFACE
UART 2
GENERAL
PURPOSE IO
(8 LINES)
ICE
NICE
INTERRUPT
CONTROLLER
DMA
CONTROLLER
TIMER /
COUNTER (x2)
REAL TIME CLOCK
MEMORY
PERIPHERAL
CONTROLLER
NSRESET
SERIAL COMMS PORT 2
GPIO / BSIO
JTAG INTERFACE
SYSTEM CLOCK
GENERATOR
WITH PLL
RESET
LOGIC
12 CHANNEL
CORRELATOR
22k
SYSTEM
SERVICES
(75)
1 PULSE PER SECOND
32kHz Crystal
TEST
IDDQTEST
(67) (70)
TIMEMARK
(69)
RAW
TIMEMARK
SERIAL COMMS PORT 1
10M
10pF 10pF
(72) (73)
RTC_
XIN
RTC_
XOUT
100k 100k 100k
10nF
100k
10nF
(17) (16)
22k
Main +3.3V
GP2015
35MHz
SAW
FILTER
175MHz
LC
FILTER
LD
CLK
MAG
SIGN
OPCLK+
OPCLK-
(15) (14) (11) (21)
PREF
(8)
1575MHz
RF
FILTER
RESET
GENERATOR
(e.g DS1818-5)
10MHz
TCXO
10k
GP4020 +3.3V
Main +3.3V
Figure 1.2 Block Diagram of typical GP4020 based GPS receiver