Data Sheet

3. I/O Multiplexing and Considerations
3.1 Multiplexed Signals
UQFN48/
TQFP48
Pin name
(1,2)
Special ADC0 AC0 USARTn SPI0 TWI0 TCA0 TCBn EVSYS CCL-LUTn
44 PA0 EXTCLK 0,TxD 0-WO0 0-IN0
45 PA1 0,RxD 0-WO1 0-IN1
46 PA2 TWI 0,XCK SDA(MS) 0-WO2 0-WO EVOUTA 0-IN2
47 PA3 TWI 0,XDIR SCL(MS) 0-WO3 1-WO 0-OUT
48 PA4 0,TxD
(3)
MOSI 0-WO4
1 PA5 0,RxD
(3)
MISO 0-WO5
2 PA6 0,XCK
(3)
SCK 0-OUT
(3)
3 PA7 CLKOUT OUT 0,XDIR
(3)
SS EVOUTA
(3)
4 PB0 3,TxD 0-WO0
(3)
5 PB1 3,RxD 0-WO1
(3)
6 PB2 3,XCK 0-WO2
(3)
EVOUTB
7 PB3 3,XDIR 0-WO3
(3)
8 PB4 3,TxD
(3)
0-WO4
(3)
2-WO
(3)
9 PB5 3,RxD
(3)
0-WO5
(3)
3-WO
10 PC0 1,TxD MOSI
(3)
0-WO0
(3)
2-WO 1-IN0
11 PC1 1,RxD MISO
(3)
0-WO1
(3)
3-WO
(3)
1-IN1
12 PC2 TWI 1,XCK SCK
(3)
SDA(MS)
(3)
0-WO2
(3)
EVOUTC 1-IN2
13 PC3 TWI 1,XDIR SS
(3)
SCL(MS)
(3)
0-WO3
(3)
1-OUT
14 VDD
15 GND
16 PC4 1,TxD
(3)
0-WO4
(3)
17 PC5 1,RxD
(3)
0-WO5
(3)
18 PC6 1,XCK
(3)
1-OUT
(3)
19 PC7 1,XDIR
(3)
EVOUTC
(3)
20 PD0 AIN0 0-WO0
(3)
2-IN0
21 PD1 AIN1 P3 0-WO1
(3)
2-IN1
22 PD2 AIN2 P0 0-WO2
(3)
EVOUTD 2-IN2
23 PD3 AIN3 N0 0-WO3
(3)
2-OUT
24 PD4 AIN4 P1 0-WO4
(3)
25 PD5 AIN5 N1 0-WO5
(3)
26 PD6 AIN6 P2 2-OUT
(3)
27 PD7 VREFA AIN7 N2 EVOUTD
(3)
28 AVDD
29 GND
30 PE0 AIN8 MOSI
(3)
0-WO0
(3)
31 PE1 AIN9 MISO
(3)
0-WO1
(3)
32 PE2 AIN10 SCK
(3)
0-WO2
(3)
EVOUTE
33 PE3 AIN11 SS
(3)
0-WO3
(3)
34 PF0 TOSC1 2,TxD 0-WO0
(3)
3-IN0
35 PF1 TOSC2 2,RxD 0-WO1
(3)
3-IN1
36 PF2 TWI AIN12 2,XCK SDA(S)
(3)
0-WO2
(3)
EVOUTF 3-IN2
37 PF3 TWI AIN13 2,XDIR SCL(S)
(3)
0-WO3
(3)
3-OUT
ATmega809/1609/3209/4809 – 48-pin
I/O Multiplexing and Considerations
© 2019 Microchip Technology Inc.
Datasheet Preliminary
DS40002016B-page 7