Data Sheet

4.12 SPI
Figure 4-4. SPI - Timing Requirements in Master Mode
MSb LSb
t
MOS
t
MIS
t
MIH
t
SCKW
t
SCK
t
MOH
t
MOH
t
SCKF
t
SCKR
t
SCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSb LSb
Figure 4-5. SPI - Timing Requirements in Slave Mode
MSb
LSb
t
SIS
t
SIH
t
SSCKW
t
SSCKW
t
SSCK
t
SSH
t
SOSH
tSSCKR
tSSCKF
t
SOS
t
SSS
t
SOSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSb
LSb
Table 4-18. SPI - Timing Characteristics
Symbol
(1)
Description Condition Min. Typ. Max. Unit
f
SCK
SCK clock frequency Master - - 10 MHz
t
SCK
SCK period Master 100 - - ns
t
SCKW
SCK high/low width Master - 0.5*SCK - ns
t
SCKR
SCK rise time Master - 2.7 - ns
t
SCKF
SCK fall time Master - 2.7 - ns
t
MIS
MISO setup to SCK Master - 10 - ns
t
MIH
MISO hold after SCK Master - 10 - ns
t
MOS
MOSI setup to SCK Master - 0.5*SCK - ns
t
MOH
MOSI hold after SCK Master - 1.0 - ns
ATmega809/1609/3209/4809 – 48-pin
Electrical Characteristics
© 2019 Microchip Technology Inc.
Datasheet Preliminary
DS40002016B-page 20