Low Distortion IMX219 M12 Mount Camera Module for Raspberry Pi - Datasheet
Table Of Contents
- Description
 - Features
 - Device Structure
 - USE RESTRICTION NOTICE
 - 1. Block Diagram and Pin Configuration
 - 2. Pixel Signal Output Specifications
 - 3. Control Registers
- 3-1 2-wire Serial Communication Operation Specifications
 - 3-2 2-wire Serial Communication Register Map (Configuration register, Parameter limit register)
 - 3-3 Parameter Limit Registers – [0x1000-0x1FFF] (Read Only and Static)
 - 3-4 Manufacturer Specific Registers – [0x3000-0x5FFF ]
 - 3-5 Frame Bank A and Bank B specific output samples
 
 - 4. Output Data Format
 - 6. On Chip Image Processing
 - 7. NVM Memory Map
 - 8. How to operate IMX219PQH5-C
 - 9. Other Functions
 - 10. Electrical Characteristics
 - 11. Spectral Sensitivity Characteristic
 - 12. Image Sensor Characteristics
 - 13. Measurement Method for Image Sensor Characteristics
 - 14. Spot Pixel Specification
 - 15. Notice on White Pixels Specifications
 - 16. Chief Ray Angle Characteristics
 - 17. Connection Example
 - 18. Notes On Handling
 
IMX219PQH5-C 
37 
3-3-1-3    Pre-PLL and PLL Clock Set-up Capability Registers – [0x1100-0x111F] 
Index 
Byte 
Register Name 
RW 
Comment 
Re-Time 
Default 
(HEX) 
Embd   
DL 
0x1100 
[7:0] 
min_ext_clk_freq_mhz   
RO 
Minimum external clock frequency 
Format: IEEE 32-bit float 
Units: MHz   
6 MHz ( = min_ext_clk_freq_mhz) 
40 
0x1101 
[7:0] 
C0 
0x1102 
[7:0] 
00 
0x1103 
[7:0] 
00 
0x1104 
[7:0] 
max_ext_clk_freq_mhz   
RO 
Maximum external clock frequency 
Format: IEEE 32-bit float Units: MHz   
27 MHz ( = max_ext_clk_freq_mhz) 
41 
0x1105 
[7:0] 
D8 
0x1106 
[7:0] 
00 
0x1107 
[7:0] 
00 
0x1108 
[7:0] 
min_pre_pll_clk_div   
RO 
Minimum Pre PLL divider value 
Format: 16-bit unsigned integer   
00 
0x1109 
[7:0] 
01 
0x110A 
[7:0] 
max_pre_pll_clk_div   
RO 
Maximum Pre PLL divider value 
Format: 16-bit unsigned integer   
00 
0x110B 
[7:0] 
0D 
0x110C 
[7:0] 
min_pll_ip_freq_mhz   
RO 
Minimum PLL input clock frequency 
Format: IEEE 32-bit float Units: MHz   
6 MHz 
40 
0x110D 
[7:0] 
C0 
0x110E 
[7:0] 
00 
0x110F 
[7:0] 
00 
0x1110 
[7:0] 
max_pll_ip_freq_mhz   
RO 
Maximum PLL input clock frequency 
Format: IEEE 32-bit float Units: MHz   
27 MHz ( = max_ext_clk_freq_mhz) 
41 
0x1111 
[7:0] 
D8 
0x1112 
[7:0] 
00 
0x1113 
[7:0] 
00 
0x1114 
[7:0] 
min_pll_multiplier   
RO 
Minimum PLL multiplier 
Format: 16-bit unsigned integer   
00 
0x1115 
[7:0] 
08 
0x1116 
[7:0] 
max_pll_multiplier   
RO 
Maximum PLL Multiplier 
Format: 16-bit unsigned integer   
07 
0x1117 
[7:0] 
FF 
0x1118 
[7:0] 
min_pll_op_freq_mhz   
RO 
Minimum PLL output clock 
frequency Format: IEEE 32-bit float 
Units: MHz   
432 MHz 
43 
0x1119 
[7:0] 
D8 
0x111A 
[7:0] 
00 
0x111B 
[7:0] 
00 
0x111C 
[7:0] 
max_pll_op_freq_mhz   
RO 
Maximum PLL output clock frequency 
Format: IEEE 32-bit float 
Units: MHz   
916 MHz 
44 
0x111D 
[7:0] 
65 
0x111E 
[7:0] 
00 
0x111F 
[7:0] 
00 










