Datasheet
Table Of Contents
- Description
- Features
- Device Structure
- USE RESTRICTION NOTICE
- 1. Block Diagram and Pin Configuration
- 2. Pixel Signal Output Specifications
- 3. Control Registers
- 3-1 2-wire Serial Communication Operation Specifications
- 3-2 2-wire Serial Communication Register Map (Configuration register, Parameter limit register)
- 3-3 Parameter Limit Registers – [0x1000-0x1FFF] (Read Only and Static)
- 3-4 Manufacturer Specific Registers – [0x3000-0x5FFF ]
- 3-5 Frame Bank A and Bank B specific output samples
- 4. Output Data Format
- 6. On Chip Image Processing
- 7. NVM Memory Map
- 8. How to operate IMX219PQH5-C
- 9. Other Functions
- 10. Electrical Characteristics
- 11. Spectral Sensitivity Characteristic
- 12. Image Sensor Characteristics
- 13. Measurement Method for Image Sensor Characteristics
- 14. Spot Pixel Specification
- 15. Notice on White Pixels Specifications
- 16. Chief Ray Angle Characteristics
- 17. Connection Example
- 18. Notes On Handling
IMX219PQH5-C
72
7-4 NVM Memory Map
Table 33 NVM Memory capacity
Capacity
data Owner
768 byte
Total
672 byte
Integrator
96 byte
Sony
Table 34 NVM Memory Map Example
Page
(dec)
Row
(dec)
Addr
(hex)
Category
Name
Value
(hex)
data
Owner
0
0-3
000 - 03F
Integrator
1
4-7
040 - 07F
Integrator
2
8-11
080 - 0BF
Integrator
3
12-15
0C0 - 0FF
Integrator
4
16-19
100 - 13F
Integrator
5
20-23
140 - 17F
Integrator
6
24-27
180 - 1BF
Integrator
7
28-31
1C0 - 1FF
Integrator
8
32-35
200 - 23F
Integrator
9
36-39
240 - 27F
Integrator
10
40-41
280 - 29F
Integrator
10
42
2A0
memcfg1
Defines availability of each data
[7:1] reserved
[0]: defect address available
Value 0x00 makes sensor skip copying data from
NVM to register.
01
Integrator
10
42
2A1
Defect Correction
defect_num[7:0]
Integrator
10
42
2A2
Defect Correction
{DFCT_SRC_10[1:0]CP_DFCT_DIR_10[1:0]
H_DFCT_ADDR_10[11:9]}
Integrator
10
42
2A3
Defect Correction
H_DFCT_ADDR_10[7:0]
Integrator
10
42
2A4
Defect Correction
V_DFCT_ADDR_10[11:4]
Integrator
10
42
2A5
Defect Correction
{V_DFCT_ADDR_10[3:0]
DFCT_SRC_11[1:0]CP_DFCT_DIR_11[1:0]}
Integrator
10
42
2A6
Defect Correction
H_DFCT_ADDR_11[11:4]
Integrator
10
42
2A7
Defect Correction
{H_DFCT_ADDR_11[3:0], V_DFCT_ADDR_11[11:8]}
Integrator
10
42
2A8
Defect Correction
V_DFCT_ADDR_11[7:0]
Integrator
10
42
2A9
Defect Correction
{DFCT_SRC_12[1:0]CP_DFCT_DIR_12[1:0]
H_DFCT_ADDR_12[11:8]}
Integrator
10
42
2AA
Defect Correction
H_DFCT_ADDR_12[7:0]
Integrator
10
42
2AB
Defect Correction
V_DFCT_ADDR_12[11:4]
Integrator
10
42
2AC
Defect Correction
{V_DFCT_ADDR_12[3:0]
DFCT_SRC_13[1:0]CP_DFCT_DIR_13[1:0]}
Integrator
10
42
2AD
Defect Correction
H_DFCT_ADDR_13[11:4]
Integrator
10
42
2AE
Defect Correction
{H_DFCT_ADDR_13[3:0], V_DFCT_ADDR_13[11:8]}
Integrator
10
42
2AF
Defect Correction
H_DFCT_ADDR_13[7:0]
Integrator
10
43
2B0
please don't write
Defect number
Sony
10
43
2B1
please don't write
Defect address (single, 2 adjacent in same color ,
2x4 static),10 address
Sony










