Datasheet

ManualsBrandsArduCAM ManualsCameras & Vision Sensors8MP IMX219 Wide Angle Camera Module for NVIDIA Jetson Nano

Table Of Contents

Description
Features
Device Structure
USE RESTRICTION NOTICE
1. Block Diagram and Pin Configuration
- 1-1 Block Diagram
- 1-2 Pin Description
- 1-3 Pin Equivalent Circuit
- 1-4 Chip Center, Optical Center and Pin Assignment
- 1-5 Pin Coordinates
2. Pixel Signal Output Specifications
- 2-1 CSI-2 Signalling Mode
  - 2-1-1 MIPI Transmitter
  - 2-1-2 Output Lane
    - 2-1-2-1 2Lane Output
3. Control Registers
- 3-1 2-wire Serial Communication Operation Specifications
- 3-2 2-wire Serial Communication Register Map (Configuration register, Parameter limit register)
- 3-3 Parameter Limit Registers – [0x1000-0x1FFF] (Read Only and Static)
  - 3-3-1 Integration Time and Gain Parameter Limit Registers – [0x1000-0x1301]
- 3-4 Manufacturer Specific Registers – [0x3000-0x5FFF ]
- 3-5 Frame Bank A and Bank B specific output samples
4. Output Data Format
- 4-1 CSI-2 Output Data Format
- 5-1 Pixel Array Physical Image
- 5-2 Pixel Binning Mode
- 5-3 image size
- 5-4 Readout Position
- 5-5 Frame Rate Calculation Formula
- 5-6 Black Level Control
- 5-7 Storage Time (Electronic Shutter) Settings
  - 5-7-1 Storage Time (Electronic Shutter) Setting Registers
  - 5-7-2 Storage Time Calculation Method
- 5-8 Gain Settings
  - 5-8-1 Analogue Gain Settings
  - 5-8-2 Digital gain settings
6. On Chip Image Processing
- 6-1 Test Pattern Generator
  - 6-1-1 Test Pattern
- 6-2 Digital Gain Setting
- 6-3 Black Level Adjust
- 6-4 Defect Correction
- 6-5 Pixel Re-alignment H Direction
- 6-6 Pixel Re-alignment V Direction
7. NVM Memory Map
- 7-1 Block Diagram
- 7-2 NVM Functions
- 7-3 Related Registers
- 7-4 NVM Memory Map
- 7-5 Defects Address registration
8. How to operate IMX219PQH5-C
- 8-1 Power on sequence
- 8-2 Power off sequence
9. Other Functions
- 9-1 Clock System
  - 9-1-1 Clock Structure
  - 9-1-2 EXCK_FREQ setting depend on INCK frequency
- 9-2 Clock Setting Example
- 9-3 Temperature Sensor
10. Electrical Characteristics
- 10-1 Absolute Maximum Ratings
- 10-2 Recommended Operating Conditions
- 10-3 Electrical Characteristics
- 10-4 AC Characteristics
  - 10-4-1 Master Clock Waveform Diagram
- 10-5 Electrical Characteristics
11. Spectral Sensitivity Characteristic
12. Image Sensor Characteristics
- 12-1 Image Sensor Characteristics
- 12-2 Zone Definition used for specifying image sensor characteristics
13. Measurement Method for Image Sensor Characteristics
- 13-1 Measurement conditions
- 13-2 Color Coding of This Image Sensor and Readout
- 13-3 Definition of Standard Imaging Conditions
- 13-4 Measurement method
14. Spot Pixel Specification
15. Notice on White Pixels Specifications
- 15-1 Measurement Method for Spot Pixels
- 15-2 Spot Pixel Pattern Specifications
16. Chief Ray Angle Characteristics
17. Connection Example
18. Notes On Handling

IMX219PQH5-C

3-1-5 Register Synchronization (Frame Bank)

Sequence for control of frame bank is explained in this section:

1. All registers on frame bank are latched by vertical synchronization (V-sync) signal.

2. Any change for registers on frame bank are reflected to functions in next frame (or following next frame) if the

corresponding registers are updated.

Figures for sequences of frame bank are shown in following statements.

-

In case that user changes following registers, we may see a term in which we do not see any output from the

sensor in addition to vertical blanking interval. From ISP's standing point, it seems that sensor has a bit longer

vertical blanking interval.

Addi-coarse_integration_time + 20[H] if fast tracking mode register is

activated.

List of registers is:

- Binning related registers (especially for analog binning)

- Sub-sampling registers (for vertical direction)

- Vertical image orientation registers

- Vertical ROI

Fig. 19 Function Example for Frame Bank