Datasheet

Table Of Contents
IMX219PQH5-C
18
Fig. 7 Start Condition
Fig. 8 Repeated Start Condition
The Stop condition is defined by SDA changing from Low to High while SCL is High.
Fig. 9 Stop Condition
Fig. 10 Slave Address
The R/W bit indicates the data transfer direction.
Table 4 R/W Bit
R/W bit
Transfer direction
0
Write (
1
Read (
After transfer of each data byte, the Master or the sensor transmits an Acknowledge / Negative Acknowledge and
releases (does not drive) SDA. When Negative Acknowledge is generated, the Master must immediately generate
the Stop condition and end the communication.
A7 A6 A5 A4 A3 A2 A1 R/WS
MSB LSB
Bus free state
Start Condition
The Data changeds
while the clock is Low.
Data sampling
SDA SCL
ACK
A7 A6 A5 A4 A3S
MSB
Start Condition
SDA SCL
ACK/NACK
The Stop condition is not generated.
D5 D4 D3 D2 D1 D0 R/W P
Bus free state
Stop Condition
SDA SCL
ACK/NACK
0
0
1
0
0
0
0
MSB
LSB
R/W
Slave Address
[7:1]
R/W
SDA
SCL
SDA
SCL
SDA
SCL