Datasheet

IMX219PQH5-C
16
2. Pixel Signal Output Specifications
IMX219PQH5-C has CSI-2 interface and the options are 4 lanes or 2lanes.
2-1 CSI-2 Signalling Mode
2-1-1 MIPI Transmitter
Output pin of CSI-2 are shown below
Fig. 4 Relationship between Output pin name and MIPI output Lane
Data and clock signals are transmitted using CSI-2 interface (high speed serial interface). Detailed explanation of
CSI-2  Interface2 (CSI-2)
Version 1.01Specification for D-PHY Version 1.1-2 interface, one bit of data is
transmitted by a pair of differential signals. In the transmitter of CSI-2 interface, differential digital signals of data or
clock are converted to differential current signals. At the receiver of CSI-2 interface, inserting output resistance,
which is serial to a pair of differential outputs (data or clock), or connecting the receiver block, which includes
internal resistance for a pair of differential outputs (data or clock), is required. In the case of using output
resistance, output resistance is placed close to the receiver. Additionally, it is recommended that each space
between differential output lines such as DMO1P/DMO1N, DMO2P/DMO2N, DMO3P/DMO3N, DMO4P/DMO4N,
or DCKP/DCKN is identical, the length of all differential output lines is same, and output line length between the
transmitter and the receiver is minimum.
2-1-2 Output Lane
Two or Four data output Lanes are applied from MIPI Alliance Standard for Camera Serial Interface2 (CSI-2)
Version 1.01.
2-1-2-1 2Lane Output
Outputs of data and clock come from CSI-2 output pins (DMO1P/DMO1N, DMO2P/DMO2N, DCKP/DCKN). A
pair of DMO1P/DMO1N is called Lane1 data and a pair of DMO2P/DMO2N is called Lane2 data. Also, clock
signals come from CSI-2 output pins, DCKP/DCKN. Maximum output data rate is 912 Mbps/lane. (1lane output
is not supported).
Lane 1
Lane 2
Clock Lane
Lane 3
Lane 4
MIPI Block
DMO1P/N
DMO2P/N
DCKP/N
DMO3P/N
DMO4P/N