Datasheet
Table Of Contents
- 1/2-Inch Megapixel CMOS Digital Image Sensor
- Applications
- General Description
- List of Tables
- List of Figures
- General Description
- Pixel Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Write and Read Sequences
- Registers
- Feature Description
- Registers
- Electrical Specifications
- Data Output and Propagation Delays
- Two-wire Serial Bus Timing
- Figure 18: Serial Host Interface Start Condition Timing
- Figure 19: Serial Host Interface Stop Condition Timing
- Figure 20: Serial Host Interface Data Timing for Write
- Figure 21: Serial Host Interface Data Timing for Read
- Figure 22: Acknowledge Signal Timing After an 8-Bit Write to the Sensor
- Figure 23: Acknowledge Signal Timing After an 8-Bit Read from the Sensor
- Quantum Efficiency
- Image Center Offset and Orientation
- Revision History
80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9M001_DS_2.fm - Rev.C 7/05 EN
9 ©2004 Micron Technology, Inc. All rights reserved.
MT9M001 - 1/2-Inch Megapixel Digital Image Sensor
Pixel Data Format
Frame Timing Formulas
Notes: 1. Row skip mode should have no effect on the integration time. Column skip mode changes
the effective value of Column Size (Reg0x04) as follows:
Column Skip 2 => R4eff = (int(R4 / 4) x 2) + 1
Column Skip 4 => R4eff = (int(R4 / 8) x 2) + 1
Column Skip 8 => R4eff = (int(R4 / 16) x 2) + 1
where the int() function truncates to the next lowest integer. Now use R4eff in the equa-
tion for row time instead of R4
2. Default for Reg0x05 = 9. However, sensor ignores any value for Reg0x05 less than 19.
Sensor timing is shown above in terms of pixel clock and master clock cycles (please
refer to Figure 6). The recommended master clock frequency is 48 MHz. The vertical
blank and total frame time equations assume that the number of integration rows (bits
13 through 0 of Reg0x09) is less than the number of active plus blanking rows (Reg0x03 +
1 + Reg0x06 + 1). If this is not the case, the number of integration rows must be used
instead to determine the frame time, as shown in Table 4.
Table 3: Frame Timing
Parameter Name Equation (MASTER CLOCK) Default Timing Notes
A Active Data Time (Reg0x04 + 1) 1,280 pixel clocks
= 26.7µs
1
P
1
Frame Start Blanking (242) 242 pixel clocks
= 5.04µs
P
2
Frame End Blanking (2 + Reg0x05 - 19)
(MIN Reg0x05 value = 19)
2 pixel clocks
= 0.042µs
2
Q = P
1
+ P
2
Horizontal Blanking (244 + Reg0x05 - 19)
(MIN Reg0x05 value = 19)
244 pixel clocks
= 5.08µs
2
A + Q Row Time ((Reg0x04 + 1) + (244 + Reg0x05 - 19)) 1,524 pixel clocks
= 31.75µs
V Vertical Blanking (Reg0x06 + 1) x (A + Q)
(MIN Reg0x06 value = 15)
39,624 pixel clocks
= 825.5µs
N
ROWS
x (A + Q) Frame Valid Time (Reg0x03 + 1) x (A + Q) 1,560,576 pixel clocks
= 32.51ms
F Total Frame Time (Reg0x03 + 1 + Reg0x06 + 1) x (A + Q) 1,600,200 pixel clocks
= 33.34ms
Table 4: Frame Time—Long Integration Time
Parameter Name Equation (master clock) Default Timing
V’
Vertical Blanking (long integration time) (Reg0x09 – Reg0x03) x (A + Q) 39,624 pixel clocks
= 82.5µs
F’
Total Frame Time (long integration time) (Reg0x09 + 1) x (A + Q) 1,600,200 pixel clocks
= 33.34ms
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