Datasheet
Table Of Contents
- 1/2-Inch Megapixel CMOS Digital Image Sensor
- Applications
- General Description
- List of Tables
- List of Figures
- General Description
- Pixel Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Write and Read Sequences
- Registers
- Feature Description
- Registers
- Electrical Specifications
- Data Output and Propagation Delays
- Two-wire Serial Bus Timing
- Figure 18: Serial Host Interface Start Condition Timing
- Figure 19: Serial Host Interface Stop Condition Timing
- Figure 20: Serial Host Interface Data Timing for Write
- Figure 21: Serial Host Interface Data Timing for Read
- Figure 22: Acknowledge Signal Timing After an 8-Bit Write to the Sensor
- Figure 23: Acknowledge Signal Timing After an 8-Bit Read from the Sensor
- Quantum Efficiency
- Image Center Offset and Orientation
- Revision History
80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9M001_DS_2.fm - Rev.C 7/05 EN
8 ©2004 Micron Technology, Inc. All rights reserved.
MT9M001 - 1/2-Inch Megapixel Digital Image Sensor
Pixel Data Format
Figure 5: Spatial Illustration of Image Readout
Output Data Timing
The data output of the MT9M001 is synchronized with the PIXCLK output. When
LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period.
Figure 6: Timing Example of Pixel Data
The rising edges of the PIXCLK signal are nominally timed to occur on the rising DOUT
edges. This allows PIXCLK to be used as a clock to latch the data. D
OUT data is valid on
the falling edge of PIXCLK. The PIXCLK is HIGH while master clock is HIGH and then
LOW while master clock is LOW. It is continuously enabled, even during the blanking
period. The parameters P1, A P2, and Q in Figure 7 are defined in Table 3.
Figure 7: Row Timing and FRAME_VALID/LINE_VALID Signals
P
0,0
P
0,1
P
0,2
.....................................P
0,n-1
P
0,n
P
1,0
P
1,1
P
1,2
.....................................P
1,n-1
P
1,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
P
m-1,0
P
m-1,1
.....................................P
m-1,n-1
P
m-1,n
P
m,0
P
m,1
.....................................P
m,n-1
P
m,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
VALID IMAGE
HORIZONTAL
BLANKING
VERTICAL BLANKING
VERTICAL/HORIZONTAL
BLANKING
LINE_VALID
PIXCLK
D
OUT
9-D
OUT
0
. . . .
. . . .
. . . .
. . . .
P
0
(9:0)
P
1
(9:0)
P2
(9:0)
P
3
(9:0)
P
4
(9:0)
P
n-1
(9:0)
P
n
(9:0)
Valid Image DataBlanking
Blanking
P1 A Q A Q AP2
. . .
. . .
. . .
Number of master clocks
FRAME_VALID
LINE_VALID
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