Datasheet
Table Of Contents
- 1/2-Inch Megapixel CMOS Digital Image Sensor
- Applications
- General Description
- List of Tables
- List of Figures
- General Description
- Pixel Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Write and Read Sequences
- Registers
- Feature Description
- Registers
- Electrical Specifications
- Data Output and Propagation Delays
- Two-wire Serial Bus Timing
- Figure 18: Serial Host Interface Start Condition Timing
- Figure 19: Serial Host Interface Stop Condition Timing
- Figure 20: Serial Host Interface Data Timing for Write
- Figure 21: Serial Host Interface Data Timing for Read
- Figure 22: Acknowledge Signal Timing After an 8-Bit Write to the Sensor
- Figure 23: Acknowledge Signal Timing After an 8-Bit Read from the Sensor
- Quantum Efficiency
- Image Center Offset and Orientation
- Revision History
80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9M001_DS_2.fm - Rev.C 7/05 EN
7 ©2004 Micron Technology, Inc. All rights reserved.
MT9M001 - 1/2-Inch Megapixel Digital Image Sensor
Pixel Data Format
Pixel Data Format
Pixel Array Structure
The MT9M001 pixel array is configured as 1,312 columns by 1,048 rows (shown in
Figure 3). The first 16 columns and the first eight rows of pixels are optically black, and
can be used to monitor the black level. The last seven columns and the last seven rows of
pixels are also optically black. The black row data is used internally for the automatic
black level adjustment. However, the black rows can also be read out by setting the sen-
sor to raw data output mode (Reg0x20, bit 11 = 1). There are 1,289 columns by 1,033 rows
of optically active pixels, which provides a four-pixel boundary around the SXGA
(1,280 x 1,024) image.
Figure 3: Pixel Array Description
Figure 4: Pixel Pattern Detail (Top Right Corner)
Output Data Format
The MT9M001 image data is read out in a progressive scan. Valid image data is sur-
rounded by horizontal blanking and vertical blanking, as shown in Figure 5. The amount
of horizontal blanking and vertical blanking is programmable through Reg0x05 and
Reg0x06, respectively. LINE_VALID is HIGH during the shaded region of the figure.
FRAME_VALID timing is described in “Output Data Timing” on page 8.
(1311, 1047)
16 black columns
7 black rows
8 black rows
(0, 0)
7 black columns
SXGA (1,280 x 1,024)
+ 4 pixel boundary
+ additional active column
+ additional active row
= 1,289 x 1,033 active pixels
Pixel
(8, 16)
black pixels
column readout direction
.
.
.
...
row
readout
direction
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