Datasheet
Table Of Contents
- 1/2-Inch Megapixel CMOS Digital Image Sensor
- Applications
- General Description
- List of Tables
- List of Figures
- General Description
- Pixel Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Write and Read Sequences
- Registers
- Feature Description
- Registers
- Electrical Specifications
- Data Output and Propagation Delays
- Two-wire Serial Bus Timing
- Figure 18: Serial Host Interface Start Condition Timing
- Figure 19: Serial Host Interface Stop Condition Timing
- Figure 20: Serial Host Interface Data Timing for Write
- Figure 21: Serial Host Interface Data Timing for Read
- Figure 22: Acknowledge Signal Timing After an 8-Bit Write to the Sensor
- Figure 23: Acknowledge Signal Timing After an 8-Bit Read from the Sensor
- Quantum Efficiency
- Image Center Offset and Orientation
- Revision History
80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9M001_DS_2.fm - Rev.C 7/05 EN
6 ©2004 Micron Technology, Inc. All rights reserved.
MT9M001 - 1/2-Inch Megapixel Digital Image Sensor
General Description
Table 2: Pin Descriptions
Pin Numbers Symbol Type Description
29 CLKIN Input
Clock in. Master clock into sensor (48 MHz maximum).
13 OE# Input
Output enable. OE# when HIGH places outputs D
OUT<0:9>,
FRAME_VALID, LINE_VALID, PIXCLK, and STROBE into a tri-state
configuration.
10 RESET# Input
Reset. Activates (LOW) asynchronous reset of sensor. All registers
assume factory defaults.
46 SCLK Input
Serial clock. Clock for serial interface.
7 STANDBY Input
Standby. Activates (HIGH) standby mode, disables analog bias circuitry
for power saving mode.
8 TRIGGER Input
Trigger. Activates (HIGH) snapshot sequence.
45 S
DATA Input/Output
Serial data. Serial data bus, requires 1.5KΩ resistor to 3.3V for pull-up.
24–28, 32–36 D
OUT<0–9> Output
Data out. Pixel data output bits 0:9, DOUT<9> (MSB), DOUT<0> (LSB).
41 FRAME_VALID Output
Frame valid. Output is pulsed HIGH during frame of valid pixel data.
40 LINE_VALID Output
Line valid. Output is pulsed HIGH during line of selectable valid pixel
data (see Reg0x20 for options).
31 PIXCLK Output
Pixel clock. Pixel data outputs are valid during falling edge of this
clock. Frequency = (master clock).
39 STROBE Output
Strobe. Output is pulsed HIGH to indicate sensor reset operation of
pixel array has completed.
15,17,18,21, 47,
48
A
GND Supply
Analog ground. Provide isolated ground for analog block and pixel
array.
5,23,38,43 D
GND Supply
Digital ground. Provide isolated ground for digital block.
16,20 V
AA Supply
Analog power. Provide power supply for analog block, 3.3V ±0.3V.
1 VAAPIX Supply
Analog pixel power. Provide power supply for pixel array, 3.3V ±0.3V
(3.3V).
4,22,37 V
DD Supply
Digital power. Provide power supply for digital block, 3.3V ±0.3V.
2,3,6,9,11,12,
14,19,30,42,44
NC —
No connect. These pins must be left unconnected.
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