Datasheet
Table Of Contents
- 1/2-Inch Megapixel CMOS Digital Image Sensor
- Applications
- General Description
- List of Tables
- List of Figures
- General Description
- Pixel Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Write and Read Sequences
- Registers
- Feature Description
- Registers
- Electrical Specifications
- Data Output and Propagation Delays
- Two-wire Serial Bus Timing
- Figure 18: Serial Host Interface Start Condition Timing
- Figure 19: Serial Host Interface Stop Condition Timing
- Figure 20: Serial Host Interface Data Timing for Write
- Figure 21: Serial Host Interface Data Timing for Read
- Figure 22: Acknowledge Signal Timing After an 8-Bit Write to the Sensor
- Figure 23: Acknowledge Signal Timing After an 8-Bit Read from the Sensor
- Quantum Efficiency
- Image Center Offset and Orientation
- Revision History
80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9M001_DS_2.fm - Rev.C 7/05 EN
27 ©2004 Micron Technology, Inc. All rights reserved.
MT9M001 - 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
.
Note:
1
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for extended periods may affect reliability.
I
STDBYD Digital standby current STDBY = VDD, CLKIN = 0 MHz
—9 20mA
I
STDBYD
W/CLK
Digital standby current STDBY = VDD, CLKIN = 48 MHz
—55 125µA
I
STDBYDA Analog standby current STDBY = VDD
—80 100µA
Table 10: AC Electrical Characteristics
(AC Setup Conditions:
f
CLKIN= 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, Output Load = 30pF,
T
A = 25°C))
Symbol Definition Condition Min Typ Max Unit
f
CLKIIN Input clock frequency
1—48MHz
t
CLKIN Input clock period
1000 — 20.83 ns
T PIXCLK period
1000 — 20.83 ns
t
R Input clock rise time
4V/ns
t
F Input clock fall time
—4 V/ns
Clock duty cycle
45/55 50/50 55/45 %
t
CP CLKIN to PIXCLK propagation delay
—10— ns
t
PD PIXCLK to data valid
——1 ns
t
PFH PIXCLK to FV high
——7 ns
t
PLH PIXCLK to LV high
——7 ns
t
PFL PIXCLK to FV low
——3 ns
t
PLL PIXCLK to LV low
——2 ns
t
OS Setup time for data before falling edge of PIXCLK
T/2 -1 T/2 T/2 +1 ns
t
OH Hold time for data after falling edge of PIXCLK
T/2 -1 T/2 T/2 +1 ns
t
FVS Setup time for FV before falling edge of PIXCLK
23—ns
t
LVS Setup time for LV before falling edge of PIXCLK
23—ns
C
LOAD Load capacitance
30 pF
Table 11: Absolute Maximum Ratings
Symbol Parameter
Rating
UnitMIN MAX
T
OP
Operating temperature
070°C
T
STG
1
Storage temperature
–40 125 °C
Table 9: DC Electrical Characteristics (continued)
(DC Setup Conditions:
f
CLKIN = 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, TA = 25°C)
Symbol Definition Condition Min Typ Max Units
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