Datasheet
Table Of Contents
- 1/2-Inch Megapixel CMOS Digital Image Sensor
- Applications
- General Description
- List of Tables
- List of Figures
- General Description
- Pixel Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Write and Read Sequences
- Registers
- Feature Description
- Registers
- Electrical Specifications
- Data Output and Propagation Delays
- Two-wire Serial Bus Timing
- Figure 18: Serial Host Interface Start Condition Timing
- Figure 19: Serial Host Interface Stop Condition Timing
- Figure 20: Serial Host Interface Data Timing for Write
- Figure 21: Serial Host Interface Data Timing for Read
- Figure 22: Acknowledge Signal Timing After an 8-Bit Write to the Sensor
- Figure 23: Acknowledge Signal Timing After an 8-Bit Read from the Sensor
- Quantum Efficiency
- Image Center Offset and Orientation
- Revision History
80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9M001_DS_2.fm - Rev.C 7/05 EN
23 ©2004 Micron Technology, Inc. All rights reserved.
MT9M001 - 1/2-Inch Megapixel Digital Image Sensor
Registers
Registers
Table 8: Black Level Registers
Register bit Description
Reg0x5F
This register controls the operation of the black level calibration thresholds.
15
No gain dependence.
1 = Thres_lo is set by the programmed value of bits 5:0, Thres_hi is reset to the programmed value
(bits 14:8) after every black level average restart.
0 = Thres_lo and Thres_hi are set automatically as described below.
14:8
Thres_hi
—maximum allowed black level in ADC LSBs (default = Thres_lo + 5).
Black level maximum is set to this value when bit 7 = 1, black level maximum is reset to this value
after every black level average restart if bit 15 = 1 and bit 7 = 0.
7
1 = override automatic Thres_hi and Thres_lo adjust (Thres_hi always = bits 14:8, Thres_lo always =
bits 5:0).
0 = automatic Thres_hi and Thres_lo adjustment.
5:0
Thres_lo
—Lower threshold for black level in ADC LSBs.
Under default automatic operation (bit 7 = 0, bit 15 = 0), Thres_lo = RegGain
max
/4 x (RegGain
max
,
bit 6 +1) x (RegGain
max
, bit 7 +1), where RegGain
max
is the maximum of the four independent gain
register settings.
Whenever a jump in the calibration causes the black level data to change from below Thres_lo to
above Thres_hi, Thres_hi is adjusted according to the following:
If new black level < 64: Thres_hi = Thres_lo + 2 + (2 x Delta), where Delta = new black level -
Thres_lo
If new black level > 63 and < 119: Thres_hi = new black level + 4
If new black level > 119: Thres_hi = 123
After any recalculation of the black level and average restart, Thres_hi is reset to either Thres_lo +
5 (automatic, default mode), Thres_hi (bit 7 = 1). Reg0x62, bit 11 will override this.
Reg0x62
This register is used to control the automatic black level calibration circuitry.
15
1 = do not perform the rapid black level sweep on new gain settings.
0 = normal operation.
14
Reserved
—default is 0; do not change.
13
Reserved
—default is 0; do not change.
12
1 = start a new running digitally filtered average for the black level (this is internally reset to “0”
immediately), and do a rapid sweep to find the new starting point.
11
1 = do not reset the upper threshold after a black level recalculation sweep.
0 = reset the upper threshold after a black level recalculation sweep (default).
10:3
Reserved
—default is 1; do not change.
2:1
Force/disable black level calibration.
00 = apply black level calibration during ADC operation only (default).
10 = apply black level calibration continuously.
X1 = disable black level correction (Offset Correction Voltage = Skew Voltage = 0.0V).
(In this case, no black level correction is possible).
0
Manual override of black level correction.
1 = override automatic black level correction with programmed values.
0 = normal operation (default).
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