Datasheet
Table Of Contents
- 1/2-Inch Megapixel CMOS Digital Image Sensor
- Applications
- General Description
- List of Tables
- List of Figures
- General Description
- Pixel Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Write and Read Sequences
- Registers
- Feature Description
- Registers
- Electrical Specifications
- Data Output and Propagation Delays
- Two-wire Serial Bus Timing
- Figure 18: Serial Host Interface Start Condition Timing
- Figure 19: Serial Host Interface Stop Condition Timing
- Figure 20: Serial Host Interface Data Timing for Write
- Figure 21: Serial Host Interface Data Timing for Read
- Figure 22: Acknowledge Signal Timing After an 8-Bit Write to the Sensor
- Figure 23: Acknowledge Signal Timing After an 8-Bit Read from the Sensor
- Quantum Efficiency
- Image Center Offset and Orientation
- Revision History
80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9M001_DS_2.fm - Rev.C 7/05 EN
15 ©2004 Micron Technology, Inc. All rights reserved.
MT9M001 - 1/2-Inch Megapixel Digital Image Sensor
Registers
Pixel Integration Control
These registers (along with the window sizing and blanking registers) control the integration time for the pixels.
The actual total integration time (
t
INT) is:
t
INT = Reg0x09 x row time - overhead time - reset delay, where:
Row time = ((Reg0x04 + 1) + 244 + Reg0x05 - 19) pixel clock periods
Overhead time = 180 pixel clock periods
Reset delay = 4 x Reg0x0C pixel clock periods
If the value in Reg0x0C exceeds (row time - 548)/4 pixel clock cycles, the row time will be extended by (4 x Reg0x0C - (row
time - 548)) pixel clock cycles.
In this expression, the row time term, Reg0x09 x ((number of columns) + 244 + horizontal blanking register - 19),
corresponds to the number of rows integrated. The overhead time (180 pixel clocks) is the overhead time between the
READ cycle and the RESET cycle, and the final term is the effect of the reset delay.
Typically, the value of Reg0x09 is limited to the number of rows per frame (which includes vertical blanking rows) such
that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the total number of rows per
frame, the MT9M001 will add additional blanking rows as needed. A second constraint is that
t
INT must be adjusted to
avoid banding in the image from light flicker. Under 60Hz flicker, this means
t
INT must be a multiple of 1/120 of a second.
Under 50Hz flicker,
t
INT must be a multiple of 1/100 of a second.
0x09 13:0
Number of rows of integration
—default = 0x0419 (1049).
0x0C 10:0
Shutter delay
—default = 0x0000 (0). This is the number of master clocks times four that the timing
and control logic waits before asserting the reset for a given row.
Frame Restart
0x0B 0
Setting bit 0 to “1” of Reg0x0B will cause the sensor to abandon the readout of the current frame
and restart from the first row. This register automatically resets itself to 0x0000 after the frame
restart. The first frame after this event is considered to be a "bad frame" (see description for
Reg0x20, bit0).
Reset
0x0D 0
This register is used to reset the sensor to its default, power-up state. To put the MT9M001 in reset
mode first write a “1” into bit 0 of this register, then write a “0” into bit 0 to resume operation.
Table 6: Register Description (continued)
Register Bit Description
元器件交易网www.cecb2b.com