Datasheet
Table Of Contents
- 1/2-Inch Megapixel CMOS Digital Image Sensor
- Applications
- General Description
- List of Tables
- List of Figures
- General Description
- Pixel Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Write and Read Sequences
- Registers
- Feature Description
- Registers
- Electrical Specifications
- Data Output and Propagation Delays
- Two-wire Serial Bus Timing
- Figure 18: Serial Host Interface Start Condition Timing
- Figure 19: Serial Host Interface Stop Condition Timing
- Figure 20: Serial Host Interface Data Timing for Write
- Figure 21: Serial Host Interface Data Timing for Read
- Figure 22: Acknowledge Signal Timing After an 8-Bit Write to the Sensor
- Figure 23: Acknowledge Signal Timing After an 8-Bit Read from the Sensor
- Quantum Efficiency
- Image Center Offset and Orientation
- Revision History
80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9M001_DS_2.fm - Rev.C 7/05 EN
12 ©2004 Micron Technology, Inc. All rights reserved.
MT9M001 - 1/2-Inch Megapixel Digital Image Sensor
Two-Wire Serial Interface Sample Write and Read Sequences
Two-Wire Serial Interface Sample Write and Read Sequences
16-Bit Write Sequence
A typical write sequence for writing 16 bits to a register is shown in Figure 8. A start bit
given by the master, followed by the write address, starts the sequence. The image sensor
will then give an acknowledge bit and expects the register address to come first, followed
by the 16-bit data. After each eight-bit transfer, the image sensor will give an acknowl-
edge bit. All 16 bits must be written before the register will be updated. After 16 bits are
transferred, the register address is automatically incremented so that the next 16 bits are
written to the next register. The master stops writing by sending a start or stop bit.
Figure 8: Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284
16-Bit Read Sequence
A typical read sequence is shown in Figure 9. First the master has to write the register
address, as in a write sequence. Then a start bit and the read address specifies that a read
is about to happen from the register. The master then clocks out the register data eight
bits at a time. The master sends an acknowledge bit after each eight-bit transfer. The reg-
ister address should be incremented after every 16 bits is transferred. The data transfer is
stopped when the master sends a no-acknowledge bit.
Figure 9: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284
SCLK
S
DATA
START ACK
0xBA ADDR
ACK ACK ACK
STOP
Reg0x09
1000 0100
0000 0010
SCLK
S
DATA
START ACK
0xBA ADDR 0xBB ADDR 0000 0010Reg0x09
ACK ACK ACK
STOP
1000 0100
NACK
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