Datasheet-1
Table Of Contents
- 1/3-Inch Wide-VGA CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- Table of Contents
- List of Figures
- List of Tables
- General Description
- Ball Descriptions
- Pixel Data Format
- Color Device Limitations
- Output Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Read and Write Sequences
- Feature Description
- Operational Modes
- Signal Path
- On-Chip Biases
- Window Control
- Blanking Control
- Pixel Integration Control
- Variable ADC Resolution
- Gain Settings
- Black Level Calibration
- Row-wise Noise Correction
- Automatic Gain Control and Automatic Exposure Control
- Pixel Clock Speed
- Hard Reset of Logic
- Soft Reset of Logic
- STANDBY Control
- Monitor Mode Control
- Read Mode Options
- LINE_VALID
- LVDS Serial (Stand-Alone/Stereo) Output
- LVDS Output Format
- Electrical Specifications
- Package Dimensions
- Appendix A – Serial Configurations
- Appendix B – Power-On Reset and Standby Timing
- Revision History
PDF: 3295348826/Source:7478516499 Aptina reserves the right to change products or specifications without notice.
MT9V022_DS - Rev.H 6/10 EN
8 ©2005 Aptina Imaging Corporation. All rights reserved.
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Ball Descriptions
Ball Descriptions
Table 3: Ball Descriptions
Only pins DOUT0 through DOUT9 may be tri-stated.
52-Ball IBGA
Numbers Symbol Type Description Note
H7 RSVD Input Connect to D
GND.1
D2 SER_DATAIN_N Input Serial data in for stereoscopy (differential negative). Tie to
1KΩ pull-up (to 3.3V) in non-stereoscopy mode.
D1 SER_DATAIN_P Input Serial data in for stereoscopy (differential positive). Tie to
D
GND in non-stereoscopy mode.
C2 BYPASS_CLKIN_N Input Input bypass shift-CLK (differential negative). Tie to 1KΩ pull-
up (to 3.3V) in non-stereoscopy mode.
C1 BYPASS_CLKIN_P Input Input bypass shift-CLK (differential positive). Tie to D
GND in
non-stereoscopy mode.
H3 EXPOSURE Input Rising edge starts exposure in slave mode.
H4 SCLK Input Two-wire serial interface clock. Connect to V
DD with 1.5K
resistor even when no other two-wire serial interface
peripheral is attached.
H6 OE Input D
OUT enable pad, active HIGH. 2
G7 S_CTRL_ADR0 Input Two-wire serial interface slave address bit 3.
H8 S_CTRL_ADR1 Input Two-wire serial interface slave address bit 5.
G8 RESET# Input Asynchronous reset. All registers assume defaults.
F8 STANDBY Input Shut down sensor operation for power saving.
A5 SYSCLK Input Master clock (26.6 MHz).
G4 S
DATA I/O Two-wire serial interface data. Connect to VDD with 1.5K
resistor even when no other two-wire serial interface
peripheral is attached.
G3 STLN_OUT I/O Output in master mode
—start line sync to drive slave chip
in-phase; input in slave mode.
G5 STFRM_OUT I/O Output in master mode
—start frame sync to drive a slave
chip in-phase; input in slave mode.
H2 LINE_VALID Output Asserted when D
OUT data is valid.
G2 FRAME_VALID Output Asserted when D
OUT data is valid.
E1 D
OUT5 Output Parallel pixel data output 5.
F1 D
OUT6 Output Parallel pixel data output 6.
F2 D
OUT7 Output Parallel pixel data output 7.
G1 D
OUT8 Output Parallel pixel data output 8
H1 DOUT9 Output Parallel pixel data output 9.
H5 ERROR Output Error detected. Directly connected to STEREO ERROR FLAG.
G6 LED_OUT Output LED strobe output.
B7 D
OUT4 Output Parallel pixel data output 4.
A8 D
OUT3 Output Parallel pixel data output 3.
A7 D
OUT2 Output Parallel pixel data output 2.
B6 D
OUT1 Output Parallel pixel data output 1.
A6 DOUT0 Output Parallel pixel data output 0.
B5 PIXCLK Output Pixel clock out. D
OUT is valid on rising edge of this clock.
B3 SHFT_CLKOUT_N Output Output shift CLK (differential negative).
B2 SHFT_CLKOUT_P Output Output shift CLK (differential positive).
A3 SER_DATAOUT_N Output Serial data out (differential negative).