Datasheet-1
Table Of Contents
- 1/3-Inch Wide-VGA CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- Table of Contents
- List of Figures
- List of Tables
- General Description
- Ball Descriptions
- Pixel Data Format
- Color Device Limitations
- Output Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Read and Write Sequences
- Feature Description
- Operational Modes
- Signal Path
- On-Chip Biases
- Window Control
- Blanking Control
- Pixel Integration Control
- Variable ADC Resolution
- Gain Settings
- Black Level Calibration
- Row-wise Noise Correction
- Automatic Gain Control and Automatic Exposure Control
- Pixel Clock Speed
- Hard Reset of Logic
- Soft Reset of Logic
- STANDBY Control
- Monitor Mode Control
- Read Mode Options
- LINE_VALID
- LVDS Serial (Stand-Alone/Stereo) Output
- LVDS Output Format
- Electrical Specifications
- Package Dimensions
- Appendix A – Serial Configurations
- Appendix B – Power-On Reset and Standby Timing
- Revision History
PDF: 3295348826/Source:7478516499 Aptina reserves the right to change products or specifications without notice.
MT9V022_DS - Rev.H 6/10 EN
7 ©2005 Aptina Imaging Corporation. All rights reserved.
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
General Description
Figure 2: 52-Ball IBGA Package
A
B
C
D
E
F
G
H
2
SER_
SHFT_
BYPASS
SER_
V
DD
D
OUT
7
FRAME
LINE_
3
SER_
SHFT_
LVDS
D
GND
STLN_
EXPO-
SURE
1
V
DD
LVDS
BYPASS
SER_
D
OUT
5
D
OUT
6
D
OUT
8
D
OUT
9
4
V
DD
V
DD
S
DATA
SCLK
6
D
OUT
0
D
OUT
1
D
GND
A
GND
LED_
OE
7
D
OUT
2
D
OUT
4
A
GND
NC
NC
V
AA
S_CTRL_
RSVD
5
SYS-
PIXCLK
STFRM_
ERROR
Top View
(Ball Down)
OUT
_VALID
8
D
OUT
3
VAAPIX
V
AA
NC
NC
STAND-
RESET#
S_CTRL
DATAO UT
_P
LVDS
_CLKIN
_P
GND
DATAIN
_P
CLKOUT
_P
DATAIN
_N
VALID
DATAO UT
_N
CLKOUT
_N
GND
OUT
LVDS
CLK
OUT
_ADR1
ADR0
BY
_CLKIN
_N