Datasheet-1

PDF: 3295348826/Source:7478516499 Aptina reserves the right to change products or specifications without notice.
MT9V022_DS - Rev.H 6/10 EN
49 ©2005 Aptina Imaging Corporation. All rights reserved.
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Appendix A – Serial Configurations
Appendix A – Serial Configurations
With the LVDS serial video output, the deserializer can be up to 8 meters from the
sensor. The serial link can save on the cabling cost of 14 wires (D
OUT[9:0], LINE_VALID,
FRAME_VALID, PIXCLK, GND). Instead, just 3 wires (2 serial LVDS, 1 GND) are sufficient
to carry the video signal.
Configuration of Sensor for Stand-Alone Serial Output with Internal PLL
In this configuration, the internal PLL generates the shift-clk (x12). The LVDS pins
SER_DATAOUT_P and SER_DATAOUT_N must be connected to a deserializer (clocked
at approximately the same system clock frequency).
Figure 46 shows how a standard off-the-shelf deserializer (National Semiconductor
DS92LV1212A) can be used to retrieve the standard parallel video signals of D
OUT(9:0),
LINE_VALID and FRAME_VALID.
Figure 46: Stand-Alone Topology
Typical configuration of the sensor:
1. Power-up sensor.
2. Enable LVDS driver (set R0xB3[4]= 0).
3. De-assert LVDS power-down (set R0xB1[1] = 0.
4. Issue a soft reset (set R0x0C[0] = 1 followed by R0x0C[0] = 0.
If necessary:
5. Force sync patterns for the deserializer to lock (set R0xB5[0] = 1).
6. Stop applying sync patterns (set R0xB5[0] = 0).
Sensor
LVDS
BYPASS_CLKIN
LVDS
SER_DATAIN
LVDS
SHIFT_CLKOUT
DS92LV1212A
82
LINE_VALID
FRAME_VALID
PIXEL
LVDS
SER_DATAOUT
26.6 MHz
Osc.
CLK
26.6 MHz
Osc.
8 meters (maximum)
8-bit configuration shown