Datasheet-1

PDF: 3295348826/Source:7478516499 Aptina reserves the right to change products or specifications without notice.
MT9V022_DS - Rev.H 6/10 EN
42 ©2005 Aptina Imaging Corporation. All rights reserved.
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Electrical Specifications
Propagation Delays for FRAME_VALID and LINE_VALID Signals
The LINE_VALID and FRAME_VALID signals change on the same rising master clock
edge as the data output. The LINE_VALID goes HIGH on the same rising master clock
edge as the output of the first valid pixel's data and returns LOW on the same master
clock rising edge as the end of the output of the last valid pixel's data.
As shown in the “Output Data Timing” on page 13, FRAME_VALID goes HIGH 143 pixel
clocks before the first LINE_VALID goes HIGH. It returns LOW 23 pixel clocks after the
last LINE_VALID goes LOW.
Figure 35: Propagation Delays for PIXCLK and Data Out Signals
Figure 36: Propagation Delays for FRAME_VALID and LINE_VALID Signals
t
PD
t
R
t
F
t
PLHP
t
HD
t
SD
SYSCLK
PIXCLK
D
OUT(9:0)
PIXCLK
FRAME_VALID
LINE_VALID
t
PFLF
t
PFLR
PIXCLK
FRAME_VALID
LINE_VALID