Datasheet-1
Table Of Contents
- 1/3-Inch Wide-VGA CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- Table of Contents
- List of Figures
- List of Tables
- General Description
- Ball Descriptions
- Pixel Data Format
- Color Device Limitations
- Output Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Read and Write Sequences
- Feature Description
- Operational Modes
- Signal Path
- On-Chip Biases
- Window Control
- Blanking Control
- Pixel Integration Control
- Variable ADC Resolution
- Gain Settings
- Black Level Calibration
- Row-wise Noise Correction
- Automatic Gain Control and Automatic Exposure Control
- Pixel Clock Speed
- Hard Reset of Logic
- Soft Reset of Logic
- STANDBY Control
- Monitor Mode Control
- Read Mode Options
- LINE_VALID
- LVDS Serial (Stand-Alone/Stereo) Output
- LVDS Output Format
- Electrical Specifications
- Package Dimensions
- Appendix A – Serial Configurations
- Appendix B – Power-On Reset and Standby Timing
- Revision History
PDF: 3295348826/Source:7478516499 Aptina reserves the right to change products or specifications without notice.
MT9V022_DS - Rev.H 6/10 EN
41 ©2005 Aptina Imaging Corporation. All rights reserved.
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Electrical Specifications
Notes: 1. This is a stress rating only, and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Notes: 1. The frequency range specified applies only to the parallel output mode of operation.
Propagation Delays for PIXCLK and Data Out Signals
The pixel clock is inverted and delayed relative to the master clock. The relative delay
from the master clock (SYSCLK) rising edge to both the pixel clock (PIXCLK) falling edge
and the data output transition is typically 7ns. Note that the falling edge of the pixel
clock occurs at approximately the same time as the data output transitions. See Table 12
for data setup and hold times.
Table 11: Absolute Maximum Ratings
Caution Stresses greater than those listed may cause permanent damage to the device.
Symbol Parameter Minimum Maximum Unit
V
SUPPLY Power supply voltage (all supplies) –0.3 4.5 V
ISUPPLY Total power supply current – 200 mA
I
GND Total ground current – 200 mA
V
IN DC input voltage –0.3 VDD + 0.3 V
VOUT DC output voltage –0.3 VDD + 0.3 V
T
STG
1
Storage temperature –40 +125 °C
Table 12: AC Electrical Characteristics
VPWR = 3.3V ±0.3V; T
A
= Ambient = 25°C; Output Load = 10pF
Symbol Definition Condition Minimum Typical Maximum Unit
SYSCLK Input clock frequency Note 1 13.0 26.6 27.0 MHz
Clock duty cycle 45.0 50.0 55.0 %
t
R Input clock rise time 1 2 5 ns
t
F Input clock fall time 1 2 5 ns
t
PLHP SYSCLK to PIXCLK propagation delay CLOAD = 10pF 3 7 11 ns
t
PD PIXCLK to valid DOUT(9:0) propagation delay CLOAD = 10pF –2 0 2 ns
t
SD Data setup time 14 16 – ns
t
HD Data hold time 14 16 –
t
PFLR PIXCLK to LINE_VALID propagation delay CLOAD = 10pF –2 0 2 ns
t
PFLF PIXCLK to FRAME_VALID propagation delay CLOAD = 10pF –2 0 2 ns










