Datasheet-1
Table Of Contents
- 1/3-Inch Wide-VGA CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- Table of Contents
- List of Figures
- List of Tables
- General Description
- Ball Descriptions
- Pixel Data Format
- Color Device Limitations
- Output Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Read and Write Sequences
- Feature Description
- Operational Modes
- Signal Path
- On-Chip Biases
- Window Control
- Blanking Control
- Pixel Integration Control
- Variable ADC Resolution
- Gain Settings
- Black Level Calibration
- Row-wise Noise Correction
- Automatic Gain Control and Automatic Exposure Control
- Pixel Clock Speed
- Hard Reset of Logic
- Soft Reset of Logic
- STANDBY Control
- Monitor Mode Control
- Read Mode Options
- LINE_VALID
- LVDS Serial (Stand-Alone/Stereo) Output
- LVDS Output Format
- Electrical Specifications
- Package Dimensions
- Appendix A – Serial Configurations
- Appendix B – Power-On Reset and Standby Timing
- Revision History
PDF: 3295348826/Source:7478516499 Aptina reserves the right to change products or specifications without notice.
MT9V022_DS - Rev.H 6/10 EN
38 ©2005 Aptina Imaging Corporation. All rights reserved.
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Feature Description
Figure 34: Serial Output Format for a 6x2 Frame
Notes: 1. External pixel values of 0, 1, 2, 3, are reserved (they only convey control information). Any raw pixel of
value 0, 1, 2 and 3 will be substituted with 4.
2. The external pixel sequence 1023, 0 1023 is a reserved sequence (conveys control information). Any raw
pixel sequence of 1023, 0, 1023 will be substituted with 1023, 4, 1023.
LVDS Output Format
In stand-alone mode, the packet size is 12 bits (2 frame bits and 10 payload bits); 10-bit
pixels or 8-bit pixels can be selected. In 8-bit pixel mode (R0xB6[0] = 0), the packet
consists of a start bit, 8-bit pixel data (with sync codes), the line valid bit, the frame valid
bit and the stop bit. For 10-bit pixel mode (R0xB6[0] = 1), the packet consists of a start
bit, 10-bit pixel data, and the stop bit.
In stereoscopic mode (see Figure 47 on page 50), the packet size is 18 bits (2 frame bits
and 16 payload bits). The packet consists of a start bit, the master pixel byte (with sync
codes), the slave byte (with sync codes), and the stop bit.)
Table 7: LVDS Packet Format in Stand-Alone Mode
(Stereoscopy Mode Bit De-Asserted)
12-Bit Packet
use_10-bit_pixels Bit De-Asserted
(8-Bit Mode)
use_10-bit_pixels Bit Asserted
(10-Bit Mode)
Bit[0] 1'b1 (Start bit) 1'b1 (Start bit)
Bit[1] PixelData[2] PixelData[0]
Bit2] PixelData[3] PixelData[1]
Bit[3] PixelData[4] PixelData[2]
Bit4] PixelData[5] PixelData[3]
Bit[5] PixelData[6] PixelData[4]
Bit[6] PixelData[7] PixelData[5]
Bit[7] PixelData[8] PixelData[6]
Bit[8] PixelData[9] PixelData[7]
Bit[9] Line_Valid PixelData[8]
Bit[10] Frame_Valid PixelData[9]
Bit[11] 1'b0 (Stop bit) 1'b0 (Stop bit)
Internal
PIXCLK
Internal
Parallel
Data
Internal
Line_Valid
Internal
Frame_Valid
External
Serial
Data Out
P41 P43P42 P44 P45 P46 P54 P55 P56P52P51 P53
1023 102301P41 P42 P46 2
1
P44P43 P45
P51 P52 P56 3P54P53 P55