Datasheet-1
Table Of Contents
- 1/3-Inch Wide-VGA CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- Table of Contents
- List of Figures
- List of Tables
- General Description
- Ball Descriptions
- Pixel Data Format
- Color Device Limitations
- Output Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Read and Write Sequences
- Feature Description
- Operational Modes
- Signal Path
- On-Chip Biases
- Window Control
- Blanking Control
- Pixel Integration Control
- Variable ADC Resolution
- Gain Settings
- Black Level Calibration
- Row-wise Noise Correction
- Automatic Gain Control and Automatic Exposure Control
- Pixel Clock Speed
- Hard Reset of Logic
- Soft Reset of Logic
- STANDBY Control
- Monitor Mode Control
- Read Mode Options
- LINE_VALID
- LVDS Serial (Stand-Alone/Stereo) Output
- LVDS Output Format
- Electrical Specifications
- Package Dimensions
- Appendix A – Serial Configurations
- Appendix B – Power-On Reset and Standby Timing
- Revision History
PDF: 3295348826/Source:7478516499 Aptina reserves the right to change products or specifications without notice.
MT9V022_DS - Rev.H 6/10 EN
36 ©2005 Aptina Imaging Corporation. All rights reserved.
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Feature Description
Interlaced Readout
The MT9V022 has two interlaced readout options. By setting R0x07[2:0] = 1, all the even-
numbered rows are read out first, followed by a number of programmable field blanking
(R0xBF, bits 7:0), and then the odd-numbered rows and finally vertical blanking
(minimum is 4 blanking rows). By setting R0x07[2:0] = 2, only one field is read out;
consequently, the number of rows read out is half what is set in R0x03. The row start
address (R0x02) determines which field gets read out; if the row start address is even, the
even field is read out; if row start address is odd, the odd field is read out.
Figure 32: Spatial Illustration of Interlaced Image Readout
When interlaced mode is enabled, the total number of blanking rows are determined by
both field blanking register (R0xBF) and vertical blanking register (R0x06). The follow-
ings are their equations.
Field Blanking = R0xBF, bits 7:0 (EQ 13)
Vertical Blanking = R0x06, bits 8:0 -R0xBF, bits 7:0 (EQ 14)
with
minimum vertical blanking requirement = 4 (EQ 15)
Similar to progressive scan, FRAME_VALID is logic LOW during the valid image row only.
Binning should not be used in conjunction with interlaced mode.
P
4,1
P
4,2
P
4,3
.....................................P
4,n-1
P
4,n
P
6,0
P
6,1
P
6,2
.....................................P
6,n-1
P
6,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
P
m-2,0
P
m-2,2
.....................................P
m-2,n-2
P
m-2,n
P
m,2
P
m,2
.....................................P
m,n-1
P
m,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ............................................................................................. 00 00 00
00 00 00 ............................................................................................. 00 00 00
VALID IMAGE - Even Field
HORIZONTAL
BLANKING
VERTICAL BLANKING
P
5,1
P
5,2
P
5,3
.....................................P
5,n-1
P
5,n
P
7,0
P
7,1
P
7,2
.....................................P
7,n-1
P
7,n
P
m-3,1
P
m-3,2
.....................................P
m-3,n-1
P
m-3,n
P
m,1
P
m,1
.....................................P
m,n-1
P
m,n
VALID IMAGE - Odd Field
FIELD BLANKING