Datasheet-1
Table Of Contents
- 1/3-Inch Wide-VGA CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- Table of Contents
- List of Figures
- List of Tables
- General Description
- Ball Descriptions
- Pixel Data Format
- Color Device Limitations
- Output Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Read and Write Sequences
- Feature Description
- Operational Modes
- Signal Path
- On-Chip Biases
- Window Control
- Blanking Control
- Pixel Integration Control
- Variable ADC Resolution
- Gain Settings
- Black Level Calibration
- Row-wise Noise Correction
- Automatic Gain Control and Automatic Exposure Control
- Pixel Clock Speed
- Hard Reset of Logic
- Soft Reset of Logic
- STANDBY Control
- Monitor Mode Control
- Read Mode Options
- LINE_VALID
- LVDS Serial (Stand-Alone/Stereo) Output
- LVDS Output Format
- Electrical Specifications
- Package Dimensions
- Appendix A – Serial Configurations
- Appendix B – Power-On Reset and Standby Timing
- Revision History
PDF: 3295348826/Source:7478516499 Aptina reserves the right to change products or specifications without notice.
MT9V022_DS - Rev.H 6/10 EN
35 ©2005 Aptina Imaging Corporation. All rights reserved.
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Feature Description
Row Binning
By setting bit 0 or 1 of R0x0D, only half or one-fourth of the row set is read out, as shown
in figure below. The number of rows read out is half or one-fourth of what is set in R0x03.
Column Binning
In setting bit 2 or 3 of R0x0D, the pixel data rate is slowed down by a factor of either two
or four, respectively. This is due to the overhead time in the digital pixel data processing
chain. As a result, the pixel clock speed is also reduced accordingly.
Figure 30: Readout of 8 Pixels in Normal and Row Bin Output Mode
Figure 31: Readout of 8 Pixels in Normal and Column Bin Output Mode
LINE_VALID
Normal readout
D
OUT
(9:0)
Row4
(9:0)
Row5
(9:0)
Row6
(9:0)
Row7
(9:0)
Row8
(9:0)
Row9
(9:0)
Row10
(9:0)
Row11
(9:0)
LINE_VALID
Row Bin 2 readout
D
OUT
(9:0)
Row4
(9:0)
Row6
(9:0)
Row8
(9:0)
LINE_VALID
Row Bin 4 readout
D
OUT
(9:0)
Row4
(9:0)
Row8
(9:0)
Row10
(9:0)
LINE_VALID
Normal readout
D
OUT(9:0)
PIXCLK
DOUT(9:0)
PIXCLK
DOUT(9:0)
PIXCLK
D1
(9:0)
D2
(9:0)
D3
(9:0)
D4
(9:0)
D5
(9:0)
D6
(9:0)
D7
(9:0)
D8
(9:0)
LINE_VALID
Column Bin 2 readout
D12
(9:0)
D34
(9:0)
D56
(9:0)
D78
(9:0)
LINE_VALID
Column Bin 4 readout
D
OUT(9:0)
d1234
(9:0)
d5678
(9:0)