Datasheet-1
Table Of Contents
- 1/3-Inch Wide-VGA CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- Table of Contents
- List of Figures
- List of Tables
- General Description
- Ball Descriptions
- Pixel Data Format
- Color Device Limitations
- Output Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Read and Write Sequences
- Feature Description
- Operational Modes
- Signal Path
- On-Chip Biases
- Window Control
- Blanking Control
- Pixel Integration Control
- Variable ADC Resolution
- Gain Settings
- Black Level Calibration
- Row-wise Noise Correction
- Automatic Gain Control and Automatic Exposure Control
- Pixel Clock Speed
- Hard Reset of Logic
- Soft Reset of Logic
- STANDBY Control
- Monitor Mode Control
- Read Mode Options
- LINE_VALID
- LVDS Serial (Stand-Alone/Stereo) Output
- LVDS Output Format
- Electrical Specifications
- Package Dimensions
- Appendix A – Serial Configurations
- Appendix B – Power-On Reset and Standby Timing
- Revision History
PDF: 3295348826/Source:7478516499 Aptina reserves the right to change products or specifications without notice.
MT9V022_DS - Rev.H 6/10 EN
34 ©2005 Aptina Imaging Corporation. All rights reserved.
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Feature Description
Read Mode Options
(Also see “Output Data Format” on page 11 and “Output Data Timing” on page 13.)
Column Flip
By setting bit 5 of R0x0D the readout order of the columns is reversed, as shown in
Figure 28 on page 34.
Row Flip
By setting bit 4 of R0x0D the readout order of the rows is reversed, as shown in Figure 29
on page 34.
Figure 28: Readout of Six Pixels in Normal and Column Flip Output Mode
Figure 29: Readout of Six Rows in Normal and Row Flip Output Mode
Pixel Binning
In addition to windowing mode in which smaller resolution (CIF, QCIF) is obtained by
selecting small window from the sensor array, the MT9V022 also provides the ability to
show the entire image captured by pixel array with smaller resolution by pixel binning.
Pixel binning is based on combining signals from adjacent pixels by averaging. There are
two options: binning 2 and binning 4. When binning 2 is on, 4 pixel signals from 2 adja-
cent rows and columns are combined. In binning 4 mode, 16 pixels are combined from 4
adjacent rows and columns. The image mode may work in conjunction with image flip.
The binning operation increases SNR but decreases resolution.
Enabling row bin2 and row bin4 improves frame rate by 2x and 4x respectively. The
feature of column binning does not increase the frame rate in less resolution modes.
LINE_VALID
Normal readout
D
OUT
(9:0)
Reverse readout
D
OUT
(9:0)
P4,1
(9:0)
P4,n
(9:0)
P4,n-1
(9:0)
P4,n-2
(9:0)
P4,n-3
(9:0)
P4,n-4
(9:0)
P4,n-5
(9:0)
P4,2
(9:0)
P4,3
(9:0)
P4,4
(9:0)
P4,5
(9:0)
P4,6
(9:0)
LINE_VALID
Normal readout
D
OUT(9:0)
Reverse readout
DOUT(9:0)
Row4
(9:0)
Row5
(9:0)
Row6
(9:0)
Row7
(9:0)
Row8
7(9:0)
Row9
(9:0)
Row484
(9:0)
Row483
(9:0)
Row482
(9:0)
Row481
(9:0)
Row480
7(9:0)
Row479
(9:0)










