Datasheet-1
Table Of Contents
- 1/3-Inch Wide-VGA CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- Table of Contents
- List of Figures
- List of Tables
- General Description
- Ball Descriptions
- Pixel Data Format
- Color Device Limitations
- Output Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Read and Write Sequences
- Feature Description
- Operational Modes
- Signal Path
- On-Chip Biases
- Window Control
- Blanking Control
- Pixel Integration Control
- Variable ADC Resolution
- Gain Settings
- Black Level Calibration
- Row-wise Noise Correction
- Automatic Gain Control and Automatic Exposure Control
- Pixel Clock Speed
- Hard Reset of Logic
- Soft Reset of Logic
- STANDBY Control
- Monitor Mode Control
- Read Mode Options
- LINE_VALID
- LVDS Serial (Stand-Alone/Stereo) Output
- LVDS Output Format
- Electrical Specifications
- Package Dimensions
- Appendix A – Serial Configurations
- Appendix B – Power-On Reset and Standby Timing
- Revision History
PDF: 3295348826/Source:7478516499 Aptina reserves the right to change products or specifications without notice.
MT9V022_DS - Rev.H 6/10 EN
30 ©2005 Aptina Imaging Corporation. All rights reserved.
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Feature Description
Registers 0x99–0x9E and 0x9F–0xA4 represent the coordinates X
0/5
-X
5/5
and Y
0/5
-Y
5/5
in
Figure 25, respectively.
Digital gains of registers 0x80
–0x98 apply to their corresponding tiles. The MT9V022
supports a digital gain of 0.25-3.75X.
The formula for digital gain setting is:
Digital Gain = Bits[3:0] x 0.25 (EQ 8)
Black Level Calibration
Black level calibration is controlled by:
•R0x4C
•R0x42
• R0x46–R0x48
The MT9V022 has automatic black level calibration on-chip, and if enabled, its result
may be used in the offset correction shown in Figure 26.
Figure 26: Black Level Calibration Flow Chart
The automatic black level calibration measures the average value of pixels from 2 dark
rows (1 dark row if row bin 4 is enabled) of the chip. (The pixels are averaged as if they
were light-sensitive and passed through the appropriate gain.)
This row average is then digitally low-pass filtered over many frames (R0x47, bits 7:5) to
remove temporal noise and random instabilities associated with this measurement.
Then, the new filtered average is compared to a minimum acceptable level, low
threshold, and a maximum acceptable level, high threshold.
If the average is lower than the minimum acceptable level, the offset correction voltage
is increased by a programmable offset LSB in R0x4C. (Default step size is 2 LSB Offset = 1
ADC LSB at analog gain = 1X.)
If it is above the maximum level, the offset correction voltage is decreased by 2 LSB
(default).
To avoid oscillation of the black level from below to above, the region the thresholds
should be programmed so the difference is at least two times the offset DAC step size.
Pixel Output
(reset minus signal)
Offset Correction
Voltage (R0x48 or
result of BLC)
10 (12) bit ADC
ADC Data
(9:0)
Gain Selection
(R0x35 or
result of AGC)
V
REF
(R0x2C)
C2
C1
S