Datasheet-1
Table Of Contents
- 1/3-Inch Wide-VGA CMOS Digital Image Sensor
- Features
- Applications
- Ordering Information
- Table of Contents
- List of Figures
- List of Tables
- General Description
- Ball Descriptions
- Pixel Data Format
- Color Device Limitations
- Output Data Format
- Serial Bus Description
- Two-Wire Serial Interface Sample Read and Write Sequences
- Feature Description
- Operational Modes
- Signal Path
- On-Chip Biases
- Window Control
- Blanking Control
- Pixel Integration Control
- Variable ADC Resolution
- Gain Settings
- Black Level Calibration
- Row-wise Noise Correction
- Automatic Gain Control and Automatic Exposure Control
- Pixel Clock Speed
- Hard Reset of Logic
- Soft Reset of Logic
- STANDBY Control
- Monitor Mode Control
- Read Mode Options
- LINE_VALID
- LVDS Serial (Stand-Alone/Stereo) Output
- LVDS Output Format
- Electrical Specifications
- Package Dimensions
- Appendix A – Serial Configurations
- Appendix B – Power-On Reset and Standby Timing
- Revision History
PDF: 3295348826/Source:7478516499 Aptina reserves the right to change products or specifications without notice.
MT9V022_DS - Rev.H 6/10 EN
24 ©2005 Aptina Imaging Corporation. All rights reserved.
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Feature Description
Window Control
Registers R0x01 column start, R0x02 Row Start, R0x03 window height (row size), and
R0x04 Window Width (column size) control the size and starting coordinates of the
window.
The values programmed in the window height and width registers are the exact window
height and width out of the sensor. The window start value should never be set below
four.
To read out the dark rows set bit 6 of R0x0D. In addition, bit 7 of R0x0D can be used to
display the dark columns in the image.
Blanking Control
Horizontal blanking and vertical blanking registers R0x05 and R0x06 respectively control
the blanking time in a row (horizontal blanking) and between frames (vertical blanking).
• Horizontal blanking is specified in terms of pixel clocks.
• Vertical blanking is specified in terms of numbers of rows.
The actual imager timing can be calculated using Table 4 on page 13 and Table 5 on
page 14 which describe “Row Timing and FRAME_VALID/LINE_VALID signals.” The
minimum number of vertical blank rows is 4.
Pixel Integration Control
Total Integration
R0x0B Total Shutter Width (In Terms of Number of Rows)
This register (along with the window width and horizontal blanking registers) controls
the integration time for the pixels.
The actual total integration time,
t
INT, is:
t
INT = (Number of rows of integration × row time) + Overhead, where:
The number of rows integration is equal to the result of automatic exposure control
(AEC) which may vary from frame to frame, or, if AEC is disabled, the value in R0x0B
Row time = (R0x04 + R0x05) master clock periods
Overhead = (R0x04 + R0x05 – 255) master clock periods
Typically, the value of R0x0B (total shutter width) is limited to the number of rows per
frame (which includes vertical blanking rows), such that the frame rate is not affected by
the integration time. If R0x0B is increased beyond the total number of rows per frame, it
is required to add additional blanking rows using R0x06 as needed. A second constraint
is that
t
INT must be adjusted to avoid banding in the image from light flicker. Under
60Hz flicker, this means frame time must be a multiple of 1/120 of a second. Under 50Hz
flicker, frame time must be a multiple of 1/100 of a second.