Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
0x4707
EOF
VSYNC_DELAY_0
0x00 RW
Bit[7:0]: eof_vsync_delay[7:0]
SOF/EOF negative edge to
VSYNC positive edge delay
0x4708 POLARITY CTRL 0x01 RW
Bit[7]: Clock DDR mode enable
Bit[6]: Not used
Bit[5]: VSYNC gate clock enable
Bit[4]: HREF gate clock enable
Bit[3]: No frst for FIFO
Bit[2]: HREF polarity reverse option
Bit[1]: VSYNC polarity reverse option
Bit[0]: PCLK polarity reverse option
0x4709 MOTO ORDER 0x00 RW
Bit[7]: FIFO bypass mode
Bit[6:4]: Data bit swap
Bit[3]: Bit test mode
Bit[2]: 10-bit bit test
Bit[1]: 8-bit bit test
Bit[0]: Bit test enable
0x470A BYP CTRL1 0x00 RW Bit[7:0]: bypass_ctrl[15:8]
0x470B BYP CTRL0 0x00 RW Bit[7:0]: bypass_ctrl[7:0]
0x470C BYP SEL 0x00 RW
Bit[7:5]: Not used
Bit[4]: href_sel
Bit[3:0]: bypass_sel
table 7-12 DVP registers (sheet 2 of 2)
address
register name
default
value
R/W
description










