Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
7-19
0x4007 BLC CTRL07 0x00 RW
Bit[7:5]: Not used
Bit[4:3]: win_sel
00: Full image
01: Windows do not contain the
first 16 pixels and the last 16
pixels
10: Windows do not contain the
first 1/16 image and the last
1/16 image
11: Windows do not contain the
first 1/8 image and the last
1/8 image
Bit[2:0]: Bypass_mode
000: Bypass data_i after limit bits
001: Bypass data_i[11:0]
011: Bypass data_i[12:1]
100: Bypass debug data bbrr
101: Bypass debug data gggg
1xx: Not used
0x4008 BLC CTRL08 0x00 RW
BLC Control
(0: disable ISP; 1: enable ISP)
Bit[7:4]: Not used
Bit[3]: flip_man_en
Bit[2]: flip_man
Bit[1]: bl_flip_man_en
Bit[0]: bl_flip_man
0x4009 BLACK LEVEL 0x10 RW Bit[7:0]: blc_blackleveltarget0
0x400A~
0x400B
DEBUG MODE – – Debug Mode
0x400C BLC MAN0 0x00 RW Bit[7:0]: blc_man0[15:8]
0x400D BLC MAN0 0x00 RW Bit[7:0]: blc_man0[7:0]
0x400E BLC MAN1 0x00 RW Bit[7:0]: blc_man1[15:8]
0x400F BLC MAN1 0x00 RW Bit[7:0]: blc_man1[7:0]
0x4010 BLC MAN2 0x00 RW Bit[7:0]: blc_man2[15:8]
0x4011 BLC MAN2 0x00 RW Bit[7:0]: blc_man2[7:0]
0x4012 BLC MAN3 0x00 RW Bit[7:0]: blc_man3[15:8]
0x4013 BLC MAN3 0x00 RW Bit[7:0]: blc_man3[7:0]
0x402C BLACK_LEVEL00 – R Bit[7:0]: blacklevel00[15:8]
0x402D BLACK_LEVEL00 – R Bit[7:0]: blacklevel00[7:0]
table 7-10 BLC registers (sheet 2 of 3)
address
register name
default
value
R/W
description










