Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
7-7
table 7-3 group hold control registers
address
register name
default
value
R/W
description
0x3200 SRM_GRUP_ADR0 0x00 RW srm_group_adr0
0x3200 GROUP ADR0 0x00 RW
Group0 Start Address in SRAM, actual
address is {0x3200[3:0], 0x0}
0x3201 GROUP ADR1 0x04 RW
Group1 Start Address in SRAM, actual
address is {0x3201[3:0], 0x0}
0x3202 GROUP ADR2 0x08 RW
Group2 Start Address in SRAM, actual
address is {0x3202[3:0], 0x0}
0x3203 GROUP ADR3 0x0B RW
Group3 Start Address in SRAM, actual
address is {0x3203[3:0], 0x0}
0x3204 GROUP LEN0 – R Length of Group0
0x3205 GROUP LEN1 – R Length of Group1
0x3206 GROUP LEN2 – R Length of Group2
0x3207 GROUP LEN3 – R Length of Group3
0x3208 GROUP ACCESS – W
Bit[7:4]: Group_ctrl
0000: Enter group write mode
0001: Exit group write mode
1010: Initiate group write
Bit[3:0]: Group ID
0000: Group 0
0001: Group 1
0010: Group 2
0011: Group 3
0x3209 DEBUG MODE – – Not Used










