Datasheet
Table Of Contents
- applications
- features
- key specifications
- table of contents
- list of figures
- list of tables
- 1 signal descriptions
- 2 system level description
- 3 block level description
- 4 image sensor core digital functions
- 4.1 mirror and flip
- 4.2 image windowing
- 4.3 test pattern
- 4.4 50/60Hz detection
- 4.5 AEC and AGC algorithms
- 4.6 AEC/AGC steps
- 4.7 black level calibration (BLC)
- 4.8 strobe flash and frame exposure
- 4.9 xenon flash control
- 4.10 frame exposure (FREX) mode
- 4.11 FREX strobe flash control
- 4.12 one-time programmable (OTP) memory
- 5 image sensor processor digital functions
- 6 image sensor output interface digital functions
- 7 register tables
- table 7-1 system control registers (sheet 1 of 5)
- table 7-2 SCCB registers (sheet 1 of 2)
- table 7-3 group hold control registers
- table 7-4 AEC/AGC 1 registers
- table 7-5 system timing registers (sheet 1 of 3)
- table 7-6 AEC/AGC 2 registers (sheet 1 of 3)
- table 7-7 STROBE/frame exposure control registers (sheet 1 of 2)
- table 7-8 50/60 HZ DETECTION registers
- table 7-9 OTP control registers (sheet 1 of 2)
- table 7-10 BLC registers (sheet 1 of 3)
- table 7-11 frame control registers
- table 7-12 DVP registers (sheet 1 of 2)
- table 7-13 MIPI top registers (sheet 1 of 11)
- table 7-14 ISPFC registers
- table 7-15 ISP TOP control registers (sheet 1 of 6)
- table 7-16 AWB registers (sheet 1 of 3)
- table 7-17 average registers (sheet 1 of 2)
- table 7-18 DPC registers
- table 7-19 LENC registers (sheet 1 of 4)
- table 7-20 cluster DPC registers (sheet 1 of 2)
- table 7-21 windows registers
- table 7-22 AEC/AGC 3 registers
- 8 operating specifications
- 9 mechanical specifications
- 10 optical specifications
- revision history
Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
0x3101 SCCB OPT 0x12 RW
Bit[7:5]: en_ss_addr_inc
Bit[4]: en_ss_addr_inc
Bit[3]: r_sda_byp_sync
0: Two clock stage SYNC for
sda_i
1: No SYNC for sda_i
Bit[2]: r_scl_byp_sync
0: Two clock stage sync for
scl_i
1: No sync for scl_i
Bit[1]: r_msk_glitch
Bit[0]: r_msk_stop
0x3102 SCCB FILTER 0x00 RW
Bit[7:4]: r_sda_num
Bit[3:0]: r_scl_num
0x3103 SCCB SYSREG 0x00 RW
Bit[7]: Not used
Bit[6]: ctrl_rst_mipisc
Bit[5]: ctrl_rst_srb
Bit[4]: ctrl_rst_sccb_s
Bit[3]: ctrl_rst_pon_sccb_s
Bit[2]: ctrl_rst_clkmod
Bit[1]: ctrl_rst_mipi_phy_rst_o
Bit[0]: ctrl_pll_rst_o
0x3104 PWUP DIS 0x01 RW
Bit[7:5]: Not used
Bit[4]: r_srb_clk_syn_en
Bit[3]: pwup_dis2
Bit[2]: pwup_dis1
Bit[1]: pll_clk_sel
Bit[0]: pwup_dis0
0x3105 PADCLK DIV 0x11 RW
Bit[7:6]: Not used
Bit[5]: sclk use p_clk_i
Bit[4]: Sleep enable
Bit[3:0]: PAD CLK divider for SCCB
0x3106 SRB CTRL 0xF9 RW
Bit[7:4]: Not used
Bit[3:2]: PLL clock divider
00: pll_sclk
01: pll_sclk/2
10: pll_sclk/4
11: pll_sclk
Bit[1]: rst_arb
0: Not used
1: Reset arbiter
Bit[0]: sclk_arb
0: Not used
1: Enable SCLK to arbiter
table 7-2 SCCB registers (sheet 2 of 2)
address
register name
default
value
R/W
description