Datasheet

Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
7-3
0x3016
SC_CMMN_MIPI_
PHY
0x00 RW
Bit[7:6]: lph
Bit[5:4]: Not used
Bit[3]: mipi_pad_enable
Bit[2]: pgm_bp_hs_en_lat
Bypass the latch of hs_enable
Bit[1:0]: ictl[1:0]
Bias current adjustment
0x3017 SC_CMMN_MIPI_PHY 0x10 RW
Bit[7:6]: pgm_vcm[1:0]
High speed common mode
voltage
Bit[5:4]: pgm_lptx[1:0]
Driving strength of low speed
transmitter 01
Bit[3]: ihalf
Bias current reduction
Bit[2]: pgm_vicd
CD input low voltage
Bit[1]: pgm_vih
CD input high voltage-dummy
Bit[0]: pgm_hs_valid
Valid delay-dummy
0x3018
SC_CMMN_MIPI_SC_
CTRL
0x58 RW
Bit[7:5]: mipi_lane_mode
0: One lane mode
1: Two lane mode
Bit[6]: r_phy_pd_mipi
0: Not used
1: Power down PHY HS TX
Bit[5]: r_phy_pd_lprx
0: Not used
1: Power down PHY LP RX
module
Bit[6]: mipi_en
0: DVP enable
1: MIPI enable
Bit[5]: mipi_susp_reg
MIPI system suspend register
0: Not used
1: Suspend
Bit[4]: lane_dis_op
0: Use mipi_release1/2 and
lane_disable1/2 to disable
two data lane
1: Use lane_disable1/2 to
disable two data lane
Bit[3:0]: Not used
0x3019
SC_CMMN_MIPI_SC_
CTRL
0x10 RW
Bit[7:0]: MIPI ULPS resume mark1 detect
length
table 7-1 system control registers (sheet 3 of 5)
address register name
default
value R/W description