Datasheet

Confidential for truly Only
11.03.2009 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies
6-21
0x4838 WKUP_DLY 0x02 RW Wakeup delay for MIPI
0x483A DIR_DLY 0v08 RW Change LP direction delay/2 after LP11
0x483C MIPI CTRL 33 0x4F RW
Bit[7:4]: t_lpx, unit: sclk cycles
Bit[3:0]: t_clk_pre, unit: sclk cycles
0x483D MIPI_T_TA_GO 0x10 RW
t_ta_go
Unit: SCLK cycles
0x483E MIPI_T_TA_SURE 0x06 RW
t_ta_sure
Unit: SCLK cycles
0x483F MIPI_T_TA_GET 0x14 RW
t_ta_get
Unit: SCLK cycles
0x4843 SNR_PCLK_DIV 0x00 RW
Bit[0]: PCLK divider
0: PCLK/SCLK = 2
and pclk_div = 1
1: PCLK/SCLK = 1
and pclk_div = 1
0x4860 MIPI CTRL 60 – R
MIPI Read/Write Only
Bit[0]: mipi_dis_me
0: Enable MIPI read/write registers
1: Disable MIPI read/write registers
0x4861 HD_SK_REG0 – R MIPI Read/Write, SCCB and MCU Read Only
0x4862 HD_SK_REG1 – R MIPI Read/Write, SCCB and MCU Read Only
0x4863 HD_SK_REG2 – R MIPI Read/Write, SCCB and MCU Read Only
0x4864 HD_SK_REG3 – R MIPI Read/Write, SCCB and MCU Read Only
0x4865 MIPI_ST – R
Bit[5]: lp_rx_sel_i
1: MIPI_LP_RX receives LP data
Bit[4]: tx_busy_i
1: MIPI_TX_LP_TX is busy to send LP
data
Bit[3]: mipi_lp_p1_i
MIPI low power input for lane 1p
Bit[2]: mipi_lp_n1_i
MIPI low power input for lane 1n
Bit[1]: mipi_lp_p2_i
MIPI low power input for lane 2p
Bit[0]: mipi_lp_n2_i
MIPI low power input for lane 2n
0x4866 T_GLB_TIM_H – R
Bit[7]: VHREF ahead of flag, must delay VHREF
Bit[6:0]: vhref_delay_h
0x4867 T_GLB_TIM_L – R vhref_delay_l
table 6-9 MIPI transmitter registers (sheet 8 of 8)
address register name
default
value R/W description