Datasheet

Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
0x4805 MIPI CTRL 05 0x10 RW
MIPI Control 05
Bit[7]: MIPI lane1 disable
1: Disable MIPI data lane1, lane1 will be
LP00
Bit[6]: MIPI lane2 disable
1: Disable MIPI data lane2, lane2 will be
LP00
Bit[5]: lpx_p_sel
0: Automatically calculate t_lpx_o in
pclkex domain, unit pclk2x
1: Use lp_p_min[7:0]
Bit[4]: lp_rx_intr_sel
0: Send lp_rx_intr_o at the first byte
1: Send lp_rx_intr_o at the end of
receiving
Bit[3]: cd_tst_sel
1: Select PHY test pins
Bit[2]: mipi_reg_mask
1: Disable MIPI access SRB
Bit[1]: clip enable
Bit[0]: hd_sk_en
0: Disable MIPI and MCU handshake
registers
1: Disable MIPI and MCU handshake
registers
0x4806 MIPI REG RW CTRL 0x28 RW
Bit[7]: prbs_en
Test mode
Bit[6]: mipi_test
Bit[5]: mipi_lp_op
0: Use new option to reduce
mipi_lptx_p
Bit[4]: two_lane_man_en
1: Use two_lane_man to manually
control two_lane_mode
Bit[3]: two_lane_man
Bit[2]: rst_rtn_en
1: Change to input to allow host RW
register after reset
Bit[1]: frame_end_en
1: After frame end packet, change to
input to allow host RW register
Bit[0]: line_end_en
1: After line end packet, change to input
to allow host RW register
0x480A MIPI BIT ORDER 0x00 RW
Bit[2]: Bit order reverse
Bit[1:0]: Bit position adjustment
01: {D[7:0],D[9:8]}
10: {D[1:0],D[9:2]}
table 6-9 MIPI transmitter registers (sheet 5 of 8)
address register name
default
value R/W description