Datasheet

Confidential for truly Only
color CMOS QSXGA (5 megapixel) image sensor with OmniBSI™ technology
OV5647
proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.0
0x4802 MIPI CTRL 02 0x00 RW
MIPI Control 02
Bit[7]: hs_prepare_sel
0: Auto calculate T_hs_prepare, unit
pclk2x
1: Use hs_prepare_min_o[7:0]
Bit[6]: clk_prepare_sel
0: Auto calculate T_clk_prepare, unit
pclk2x
1: Use clk_prepare_min_o[7:0]
Bit[5]: clk_post_sel
0: Auto calculate T_clk_post, unit
pclk2x
1: Use clk_post_min_o[7:0]
Bit[4]: clk_trail_sel
0: Auto calculate T_clk_trail, unit pclk2x
1: Use clk_trail_min_o[7:0]
Bit[3]: hs_exit_sel
0: Auto calculate T_hs_exit, unit pclk2x
1: Use hs_exit_min_o[7:0]
Bit[2]: hs_zero_sel
0: Auto calculate T_hs_zero, unit pclk2x
1: Use hs_zero_min_o[7:0]
Bit[1]: hs_trail_sel
0: Auto calculate T_hs_trail, unit pclk2x
1: Use hs_trail.min_o[7:0]
Bit[0]: clk_zero_sel
0: Auto calculate T_clk_zero, unit
pclk2x
1: Use clk_zero_min_o[7:0]
0x4803 MIPI CTRL 03 0x50 RW
MIPI Control 03
Bit[7:6]: lp_glitch_nu
0: Use 2d of lp_in
1: Mask one sclk cycle glitch of lp_in
Bit[5:4]: cd_glitch_nu
0: Use 2d of lp_cd_in
1: Mask one SCLK cycle glitch of
lp_cd_in
Bit[3]: Enable CD plus of data lane1
0: Disable
1: Enable
Bit[2]: Enable CD plus of data lane2
0: Disable
1: Enable
Bit[1]: Enable CD of data_lane1 from PHY
0: Disable
1: Enable
Bit[0]: Enable CD of data_lane2 from PHY
0: Disable
1: Enable
table 6-9 MIPI transmitter registers (sheet 3 of 8)
address register name
default
value R/W description